CN1041566C - 超标量处理器系统中分配和执行非顺序指令的方法和系统 - Google Patents

超标量处理器系统中分配和执行非顺序指令的方法和系统 Download PDF

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Publication number
CN1041566C
CN1041566C CN94100121A CN94100121A CN1041566C CN 1041566 C CN1041566 C CN 1041566C CN 94100121 A CN94100121 A CN 94100121A CN 94100121 A CN94100121 A CN 94100121A CN 1041566 C CN1041566 C CN 1041566C
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China
Prior art keywords
mentioned
instruction
distribution
scalar instruction
scalar
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Expired - Fee Related
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CN94100121A
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English (en)
Chinese (zh)
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CN1092881A (zh
Inventor
詹姆斯·A·卡勒
多纳尔德·E·沃尔德克
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
CN94100121A 1993-01-08 1994-01-06 超标量处理器系统中分配和执行非顺序指令的方法和系统 Expired - Fee Related CN1041566C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US189093A 1993-01-08 1993-01-08
US08/001,890 1993-01-08

Publications (2)

Publication Number Publication Date
CN1092881A CN1092881A (zh) 1994-09-28
CN1041566C true CN1041566C (zh) 1999-01-06

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ID=21698307

Family Applications (1)

Application Number Title Priority Date Filing Date
CN94100121A Expired - Fee Related CN1041566C (zh) 1993-01-08 1994-01-06 超标量处理器系统中分配和执行非顺序指令的方法和系统

Country Status (7)

Country Link
US (1) US6209081B1 (2)
EP (1) EP0606643A1 (2)
JP (1) JP2843750B2 (2)
KR (1) KR0122527B1 (2)
CN (1) CN1041566C (2)
CA (1) CA2107305A1 (2)
TW (1) TW242672B (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100395700C (zh) * 2004-11-01 2008-06-18 威盛电子股份有限公司 限制指令宽度处理器中增加寄存器寻址空间的系统与方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546554A (en) * 1994-02-02 1996-08-13 Sun Microsystems, Inc. Apparatus for dynamic register management in a floating point unit
US5559976A (en) * 1994-03-31 1996-09-24 International Business Machines Corporation System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions
TW295646B (2) * 1995-01-25 1997-01-11 Ibm
KR100384875B1 (ko) * 1995-12-16 2003-08-21 주식회사 하이닉스반도체 파이프라인구조를갖는마이크로프로세서에서의언세이프처리마이크로시퀀서
US6543003B1 (en) * 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor
US7814490B2 (en) 2004-10-14 2010-10-12 International Business Machines Corporation Apparatus and methods for performing computer system maintenance and notification activities in an opportunistic manner
US7734897B2 (en) * 2005-12-21 2010-06-08 Arm Limited Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads
US7921279B2 (en) * 2008-03-19 2011-04-05 International Business Machines Corporation Operand and result forwarding between differently sized operands in a superscalar processor
US9336003B2 (en) * 2013-01-25 2016-05-10 Apple Inc. Multi-level dispatch for a superscalar processor
US20140281413A1 (en) * 2013-03-14 2014-09-18 Mips Technologies, Inc. Superforwarding Processor
US10372458B2 (en) 2015-04-01 2019-08-06 Huawei Technologies Co., Ltd Method and apparatus for a self-clocked, event triggered superscalar processor
US10275250B2 (en) * 2017-03-06 2019-04-30 Arm Limited Defer buffer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106670A2 (en) * 1982-10-13 1984-04-25 Honeywell Information Systems Inc. CPU with multiple execution units
EP0381471A2 (en) * 1989-02-03 1990-08-08 Digital Equipment Corporation Method and apparatus for preprocessing multiple instructions in a pipeline processor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581246A (ja) * 1981-06-26 1983-01-06 Fujitsu Ltd 命令処理順序制御方式
JPS58178464A (ja) * 1982-04-14 1983-10-19 Hitachi Ltd 並列演算処理装置
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
EP0312764A3 (en) * 1987-10-19 1991-04-10 International Business Machines Corporation A data processor having multiple execution units for processing plural classes of instructions in parallel
US5003462A (en) * 1988-05-31 1991-03-26 International Business Machines Corporation Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means
JP2858140B2 (ja) * 1988-10-19 1999-02-17 アポロ・コンピューター・インコーポレーテッド パイプラインプロセッサ装置および方法
WO1990010267A1 (en) * 1989-02-24 1990-09-07 Nexgen Microsystems Distributed pipeline control for a computer
US5197138A (en) * 1989-12-26 1993-03-23 Digital Equipment Corporation Reporting delayed coprocessor exceptions to code threads having caused the exceptions by saving and restoring exception state during code thread switching

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106670A2 (en) * 1982-10-13 1984-04-25 Honeywell Information Systems Inc. CPU with multiple execution units
EP0381471A2 (en) * 1989-02-03 1990-08-08 Digital Equipment Corporation Method and apparatus for preprocessing multiple instructions in a pipeline processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100395700C (zh) * 2004-11-01 2008-06-18 威盛电子股份有限公司 限制指令宽度处理器中增加寄存器寻址空间的系统与方法

Also Published As

Publication number Publication date
KR0122527B1 (ko) 1997-11-20
EP0606643A1 (en) 1994-07-20
JPH06236275A (ja) 1994-08-23
CA2107305A1 (en) 1994-07-09
US6209081B1 (en) 2001-03-27
TW242672B (2) 1995-03-11
CN1092881A (zh) 1994-09-28
JP2843750B2 (ja) 1999-01-06
KR940018743A (ko) 1994-08-18

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Granted publication date: 19990106

Termination date: 20100208