CN1114948C - Semiconductor chip package having combined structure of lead-on-chip leads and standard normal leads - Google Patents

Abstract

A semiconductor chip package includes a central electrode pad and peripheral electrode pads on an active surface of an integrated circuit (IC). The package also includes a lead frame having: a first inner lead mounted directly to the active surface and connected to a central electrode pad; a second inner lead away from the chip and connected to a peripheral electrode pad; an outer lead connected to the first inner lead; and a second outer lead connected to the second inner lead. A dual row type or a quadrilateral package can be formed by arranging the second outer leads along the long side of the chip or along the short side of the IC.

Description

A semiconductor chip package with a combined structure of on-chip leads and standard conventional leads

technical field

The present invention relates generally to semiconductor chip packaging, and more particularly to methods of arranging contact leads in high density semiconductor chips.

Background technique

Generally, a semiconductor chip has a plurality of electrode pads on its active surface to facilitate connection of electrical signals between integrated circuit elements and the outside. Depending on the arrangement of the electrode pads, semiconductor chips can be divided into central pad type devices and peripheral pad type devices, wherein in the central pad type devices, the electrode pads are distributed in the central area of the active surface of the chip, and in the peripheral pad type devices. In pad-type devices, the electrode pads are arranged along the edge of the active surface of the chip. Central pad devices exhibit small signal deviations, high signal transmission speeds due to shortened bus lines, and are simple and relatively easy in terms of electrode pad design. Furthermore, semiconductor memory chips produced with a central pad design are approximately 4% to 7% smaller in size than peripheral memory chips, resulting in an increased number of net pads placed on a single wafer and thus increased throughput. Because of these and other advantages, center pad type chips are now widely used by manufacturers of memory devices.

In order to package central pad type devices, either lead-on-chip (LOC) design schemes or long-wire bonding schemes can be used, wherein the leads on the chip are directly attached to the active surface of the chip, and the long-lead bond The combination is that the leads are far away from the edge of the chip and are connected to the electrode pads through long bonding wires. However, the latter has some problems such as poor reliability due to such long bonding wires. On the other hand, although LOC wires require more manufacturing cost than standard conventional wires, the bonding wires can be made shorter and thus improve the reliability of the package. In turn, the LOC package can increase the size of the chip to the total package. The ratio.

Nevertheless, due to the ever-increasing density of memory chips, packaging engineers are faced with some technical problems, that is, because the manufacturing technology of the lead frame cannot keep up with the shrinking ratio of the chip, all the LOC leads are placed on the next generation memory chip. Shrinking the active surface is not possible. Typically, leadframe leads are patterned either by stamping or by photoetching. In these two methods, only when the width of the lead or the distance between adjacent leads is equal to or greater than 80% of the thickness of the lead frame, can an ideal lead pattern be produced. In order to overcome this limitation, reducing the thickness of the lead frame can be considered, however, this design scheme is not ideal, because the thin lead frame is extremely fragile and the leads of this pattern are easily damaged during the assembly process, Even due to a small shock.

Therefore, it is necessary to package high-density semiconductor chips without losing the advantages of the central pad structure and the LOC lead structure.

Contents of the invention

An object of the present invention is to provide a semiconductor chip package capable of mounting high-density semiconductor chips by using a center pad structure and an LOC lead structure.

Another object of the present invention is to provide a semiconductor chip package capable of overcoming the limitations of lead frame production and efficiently packaging high-density semiconductor chips.

In the semiconductor chip package according to the present invention, the semiconductor chip has a combination type bonding of the central pad, and the lead frame is provided with a plurality of first inner leads which are directly mounted to the active surface of the chip and electrically connected to the central electrode pad and a plurality of second inner leads distributed away from the edge of the chip and electrically connected to the peripheral electrode pads.

Generally, a semiconductor chip is rectangular with a long side and a short side. When the outer lead and the inner lead of the lead frame are integrated and distributed along both the long side and the short side, a quadrilateral shape can be obtained. packaged device, and if the outer leads are distributed along the long side of the chip, a dual row type packaged device is obtained.

The lead frame applied to the package of the present invention includes tie bars that connect between the corner leads and the side rails of the lead frame so that the individual packages can be held in strips during assembly until they become a single body, and the longest The corner leads can be supported and protected from damage. The lead frame may further include alignment keys to improve recognizability and accurate placement of the lead frame and semiconductor chip when the chip is attached to the leads of the lead frame and when the leads are electrically connected to the electrode pads.

The first inner lead of the LOC structure has an up-set region, the size of which is determined by the thickness of the chip and the thickness of the adhesive used to attach the chip to the first lead, by controlling the Depending on the size of the inclined area, it is possible to obtain the best vertical structure of the packaged device.

Description of drawings

Some objects and advantages of the present invention have been described above, through the following detailed description, and with reference to the accompanying drawings, other objects and advantages will be more fully understood, wherein:

Figure 1 is a partial plan view of a preferred leadframe strip of the present invention;

2 is a plan view of a semiconductor chip package according to one embodiment of the present invention;

3 is a partial plan view of a semiconductor chip package according to the present invention;

Fig. 4A is a sectional view taken along line IV-A in Fig. 2;

Fig. 4B is a sectional view taken along line IV-B in Fig. 2;

5 is a cross-sectional view of a semiconductor chip package according to another embodiment of the present invention;

6 is a perspective view of an exemplary semiconductor chip package of the present invention;

7 is a partial plan view of a semiconductor chip package according to yet another embodiment of the present invention; and

FIG. 8 is a perspective view of a semiconductor chip package according to yet another embodiment of the present invention.

Detailed ways

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 is a partial plan view of a preferred leadframe strip of the present invention. Leadframe strip 100 has several identical leadframe patterns, thereby enabling die bonding, wire bonding, and molding processes to be applied to multiple chips. During assembly, leadframe strips 100 are conveyed through the use of conveyance holes 16, the repeating individual leadframe patterns being separated by slots 22, only one single leadframe pattern being shown in FIG. 1 for simplicity.

Each single pattern has a plurality of inner leads 10 and 12 electrically connected to electrode pads of a semiconductor chip (not shown), and a plurality of outer leads 14a and 14b for electrically connecting the chip, the inner leads and the outer leads Coupled by the stop bar 28, when the plastic molding resin fills the molding area 34 to form a package protection body, the stop bar 28 will prevent the overflow of the molding resin. After the molding process, the bar 28 and the tie rod 18 are cut away so that the inner and outer leads are independent.

By means of the side rails 24, each single lead frame pattern is made into a strip shape, and the corner leads 15 located at the four corners of the molding area 34 are connected to the side rails 24 through the connecting rods 18. When the blocking strip 28 is cut When the single lead frame does not finally become a single body, the connecting rod 18 connecting the corner lead 15 and the side rail 24 is used to support the single lead frame, and the connecting rod 18 can prevent any possible deformation of the corner lead 15, The corner leads 15 have the longest length and thus are easily damaged and deformed during assembly.

The leads 20 are not called connecting leads, they are not connected to the chip, the power supply leads 26 are channels for the positive power supply voltage VDD and the negative power supply voltage VSS applied to the chip, and the power supply leads 26 are divided into two parts so as to reduce the number of leads inductance.

For leadframe leads, the first inner lead 10 is a LOC lead and the second inner lead is a standard conventional lead. The first inner lead 10 is directly attached to the active surface of the chip through an adhesive material 32, and it has a bending area (slope area) 30. This combined lead structure is suitable for packaging with centrally distributed electrode pads and peripherally distributed The electrode pads of the semiconductor chip.

FIG. 2 is a plan view of a semiconductor chip package according to one embodiment of the present invention. In FIG. 2, the semiconductor chip package 200 has a total of one hundred input/output pins, each of which transmits and receives different signals.

Semiconductor chip 40 has a long side 42 and a short side 44, a rectangular configuration that is common in semiconductor memory chips. On the active surface 46 of the semiconductor chip 40, many internal circuit elements such as memory cells, control gates, metal lines, and a plurality of electrode pads 48 and 49 are formed. The electrode pads include a central electrode pad 48 and peripheral electrodes. The pads 49, wherein the electrode pads 48 are arranged in two rows and parallel to the long side 42 above the central area of the active surface 46 of the chip, and the electrode pads 49 are arranged along the short side near the edge of the active surface 46 of the chip. 44 while distributed.

The first LOC inner lead 10 is arranged along the long side 42 of the chip and is directly attached to the active surface 46 of the chip by the adhesive 32, and the first inner lead 10 is electrically connected to the central electrode pad by the bonding wire 52 48, and electrically connected to the first outer lead 14a, and the outer lead 14a is also distributed along the long side 42 as well.

Adhesive 32 is electrically insulating, and may be a double-sided adhesive made of polyimide, or using adhesive tape or depositing a partially cured adhesive, the semiconductor chip can be bonded to the first inner layer. on the lead. In the former case, the tape is bonded to the first inner lead, which is then aligned with and disposed on the active surface of the chip. By applying pressure to the first inner lead and the chip at high temperature, the two are bonded together. Meanwhile, the die bonding operation can be performed by depositing a partially cured liquid adhesive material on the active surface of the chip, and then by pressing the first inner lead and the chip at high temperature.

The second inner leads 12 are arranged along the short side 44 of the semiconductor chip and have a standard conventional structure, ie they are away from the edge of the chip. The second inner lead 12 is electrically connected to the peripheral electrode pad 49 through the bonding wire 52 and is connected to the second outer lead 14b distributed along the short side 44 of the chip.

For this combined structure of LOC leads and standard leads, it is possible to overcome the limitation of the processing process of the lead frame, so that high-density memory devices can be packaged effectively. The advantages of the central type, such as small signal deviation, high signal transmission rate, and simplicity and relative ease in the design of the electrode pads can thus also be obtained.

As shown in FIG. 2, the peripheral electrode pad 49 and the adhesive 32 must be separated by a distance D. The distance D is determined after considering several parameters, such as the processing tolerance of the lead frame and the processing tolerance in the packaging process. , and the contact between the first inner lead and the capillary for wire bonding, it is preferable to keep the distance D equal to or greater than 20 mils.

The dummy leads 20 whose pin numbers are 36-45 and 86-96 are not connection leads, they are due to, for example, the difference between the number specification of the outer leads defined by JEDEC and the real number of outer leads for the function of a certain memory device. resulting from differences.

The first inner lead 10 may include an alignment key 50 which is used to help identify the position of the leadframe leads and the memory chip 40 during the die bonding process as well as the wire bonding process. Either etched or stamped, the alignment key 50 can be made at the same time as the leadframe pattern and is naturally formed of the same material as the leadframe strip.

The power lead 26 provides power supply voltages such as VDD and VSS for the memory chip 40, and its ends are divided into two parts. These two parallel power supply channels reduce the inductance between the lead frame leads, thereby providing a relatively stable power supply. .

For this stable power supply, the bus structure shown in Figure 3 can be used. Referring to FIG. 3, the bus bar 56 connects inner leads and forms a single channel through which a constant power supply voltage is applied. Therefore, a constant level of power supply voltage can be applied to different circuit elements, and the noise effect of the power supply can be reduced. In FIG. It is used to receive negative VSS power supply voltage signal, and the inner leads with pin numbers 59, 67, 73 and 79 are connected by bus bus bar 56b, wherein the positive VDD power supply voltage signal is applied to bus bus bar 56b.

As shown in FIG. 2 , when the first inner leads 10 are mounted on the active surface 46 of the chip, the first inner leads must be distributed so as not to be placed on the fuse box 54 . The fuse box 54 typically provides a storage unit for replacing a failed storage device with a redundant unit, and has exposed metal wires, such as aluminum wires, which can be cut by a laser. If the fuse box 54 is covered by the first inner lead, it becomes impossible to repair the failed memory cell.

As shown in FIG. 4A , the first inner lead 10 has an inclined region 30 , which is a cross-sectional view taken along line IVA in FIG. 2 . The sloped area 30 places the semiconductor chip 40 in the central portion of the protective package 60 . For example, if the semiconductor chip has a size of 197 mils by 340 mils and a thickness of 0.3 mils, and the thickness t of the adhesive is 0.1 mils, the size of the beveled region 30 may be about 0.2 mils so that the The distance d1 from the semiconductor chip to the top surface of the package is 1.05 mils, which is substantially equal to the distance d2 from the semiconductor chip to the bottom surface of the package. The protective package is formed by a molding process in which liquid molding resin is injected under high pressure into the cavity in which the leadframe strip is placed, at which point, if the distances d1 and d2 are different, the The injection force of the molding resin is unbalanced at the upper and lower parts of the package, and thus, tilting of the semiconductor chip may occur, which causes warpage of the package in the subsequent assembly process, however, in this In the invention, because the balance of the upper and lower parts of the package can be adjusted by controlling the size of the inclined area 30, the inclined area 30 is formed in the first inner lead 10, so that the best vertical structure of the package can be obtained, although the inclined The size of region 30 is depicted as approximately 0.2 mils, and those of ordinary skill in the art will appreciate that this size may vary depending on the thickness of the semiconductor chip and the thickness of the adhesive.

4B is a cross-sectional view taken along line IVB in FIG. The second inner leads 12 are standard conventional leads which are arranged away from the semiconductor chip 40 .

As shown in FIGS. 2 and 4B, the semiconductor chip package 200 has inner leads 10 and 12, which are electrically connected to electrode pads 48 and 49 by bonding wires 52. An inner lead 10 can also be electrically connected to the central electrode pad 48 by using metal bumps instead of bonding wires.

5 is a cross-sectional view of a semiconductor chip package according to an embodiment of the present invention. Referring to FIG. Connected to the central electrode pad 48, the metal bump 70 is formed on the electrode pad 48, the metal bump 70 can be a gold bump, a copper bump or a tin-lead bump, the metal bump 70 is connected to the first The inner lead 10 is bonded by thermo-compression method, at this time, attention must be paid to the precise alignment of the lead and the electrode pad. Although not shown in FIG. 5 , in order to improve the bonding force between the first inner lead 10 and the semiconductor chip 40 , an adhesive may be used.

FIG. 6 is a perspective view of a semiconductor chip package according to another embodiment of the present invention. The semiconductor chip package 300 is a quadrilateral package, wherein the outer leads 14 protrude along the four sides of the package body 60, and the outer leads 14 are shaped as a gull-wing or a J-type lead so that the package 300 can be surface mounted to a circuit board (not shown). shown) above. The quad package is suitable for chips having many input/output pins, and it represents an increased packing density compared to pin-insert type packages.

By arranging the first outer lead 14a along the long side 42 of the semiconductor chip 40 and setting the second outer lead 14b along the short side 44 of the chip 40, this quadrangular packaging device can be obtained, as shown in Figures 1 and 2 Show.

7 is a plan view of a semiconductor chip package according to another embodiment of the present invention, similar to the embodiment shown in FIG. 2, the semiconductor chip package 400 shown in FIG. 7 includes a first inner lead 110 of a LOC structure, and Mounted directly on the active surface 146 of the chip and electrically connected to the central electrode pad 149, the package also includes standard second inner leads 112 distributed away from the short side 144 of the semiconductor chip 140 and electrically connected to the peripheral electrode pads 149. Disk 149.

The first inner lead 110 of the package 400 has a sloped area for establishing an optimal vertical structure of the package and is bonded to the active surface 146 of the chip by the adhesive 132 . Adhesive 132 must be at least 20 mils from perimeter electrode pad 149 . The power lead 126 is divided into two parts, and although the power lead 126 is distributed in the second inner lead as in FIG. 7, it is possible to form the power lead in the first inner lead.

Tie rods 180 are also encapsulated by the protective encapsulation and are attached to the side rails of the leadframe strips to serve to hold the individual leadframe patterns in the strip shape prior to forming a unitary body, the first and The second inner leads 110 and 112 are electrically connected to the electrode pads, as shown in FIG. 7 . Nevertheless, the first inner lead 110 can also be electrically connected to the central electrode pad 148 by using metal bumps, similar to the embodiment described above with reference to FIG. 5 .

Whether it is the first outer lead 114a connected to the first inner lead 110 or the second outer lead 114b connected to the second inner lead 112, they are all distributed along the long side of the protective package. Outer leads, a dual inline package 400 as shown in FIG. 8 can be obtained, wherein the outer leads protrude from the two long sides of the package, and the outer leads 114 have gull-wing-shaped ends, as shown in FIG. 8 , or Has J-lead terminations for surface-mounting of package 400.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the described examples, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims (21)

1. semiconductor die package comprises:

Semiconductor chip, it has long limit and minor face and integrated circuit component active surface formed thereon, described semiconductor chip has a plurality of contre electrode pads and a plurality of peripheral electrode pad, wherein the contre electrode pad is positioned on the middle section on described active surface and distributes along described long limit, and the peripheral electrode pad then is positioned on the neighboring area on described active surface and distributes along described minor face;

Lead frame, it has a plurality of leads and a plurality of outer lead, so that make described semiconductor chip be electrically connected to external devices, described lead comprises first lead and second lead, wherein first lead directly mounts to the described active surface of described semiconductor chip and along described long limit and arranges, second lead along and arrange away from described minor face, described outer lead comprises first outer lead and second outer lead, wherein first outer lead is connected with described first lead and arranges along described long limit, and second outer lead is connected with described second lead and arranges along described minor face;

Electrical connection is used for described first lead is connected to described contre electrode pad and described second lead is connected to described peripheral electrode pad; And

The protectiveness packaging body is used to seal described semiconductor chip, and described first and described second lead, and described electrical connection.

2. semiconductor die package as claimed in claim 1, it is characterized in that, described lead frame also comprises the bight lead-in wire, be positioned at the bight on the described active surface of described semiconductor chip, and described bight lead-in wire is by link supports, this connecting rod is connected on the siding track of lead-in wire moulding, and this lead-in wire moulding comprises described lead frame.

3. semiconductor die package as claimed in claim 1, it is characterized in that, described a plurality of first lead comprises alignment keys, when described semiconductor chip mounts to described first lead and when described first when being connected with described electrode pad by described electrical connection with described second lead, this alignment keys is used for described lead frame is aimed at described semiconductor chip.

4. semiconductor die package as claimed in claim 1 is characterized in that described electrical connection is a bonding line.

5. semiconductor die package as claimed in claim 1, it is characterized in that described electrical connection comprises metal salient point, be used to connect described a plurality of lead and described contre electrode pad, and bonding line, be used to connect described a plurality of second lead and described peripheral electrode pad.

6. semiconductor die package as claimed in claim 1 is characterized in that, described contre electrode pad distributes according to two parallel lines, and these two parallel lines are arranged essentially parallel to the described long limit of described semiconductor chip.

7. semiconductor die package as claimed in claim 1 is characterized in that, described a plurality of first leads have tilting zone.

8. semiconductor die package as claimed in claim 1 is characterized in that described lead comprises the power supply lead, and this power supply lead is divided into two parts.

9. semiconductor die package as claimed in claim 1 is characterized in that, described first lead mounts to described active surface by electrical insulating tape.

10. semiconductor die package as claimed in claim 9 is characterized in that, described adhesive tape is the two-sided tape that is made into by polyimides.

11. semiconductor die package as claimed in claim 9; it is characterized in that; described first lead has tilting zone; and the size of described tilting zone is determined by the thickness of described adhesive tape and the thickness of described semiconductor chip, so that make described semiconductor chip be positioned at the central authorities of described protectiveness packaging body.

12. semiconductor die package as claimed in claim 9 is characterized in that, the distance of the described adhesive tape of described peripheral electrode pad distance is greater than 20 mils.

13. semiconductor die package as claimed in claim 1 is characterized in that, described first lead comprises the bus bars that is used to connect power supply lead wire, is provided in the described semiconductor chip by this power supply lead wire stabilized power source voltage signal.

14. semiconductor die package as claimed in claim 1, it is characterized in that, described semiconductor chip has a plurality of safety boxs, they are formed on the described active surface, described safety box with the metal wire that exposes that can be cut off by laser beam is to be used for replacing with good unit the trouble unit of described semiconductor chip, and wherein said first lead directly mounts to described active surface and but do not cover described safety box.

15. a semiconductor die package comprises:

Semiconductor chip, has long limit and minor face and internal circuit unit active surface formed thereon, described semiconductor chip has a plurality of contre electrode pads and a plurality of peripheral electrode pad, wherein the contre electrode pad is positioned on the middle section on described active surface and distributes along described long limit, and the peripheral electrode pad is positioned on the neighboring area on described active surface and distributes along described minor face;

Lead frame, have a plurality of leads and a plurality of outer lead, described outer lead and described lead form as a whole, and be used to make described semiconductor chip to be electrically connected to external devices, described lead comprises first lead and second lead, wherein first lead directly mounts to the described active surface of described semiconductor chip, and arrange along described long limit, second lead along and arrange away from described minor face, described outer lead comprises first outer lead and second outer lead, wherein first outer lead is connected with described first lead and arranges along described long limit, and second outer lead is connected with described second lead and arranges along described long limit;

Electrical connection is used for described first lead is connected to described contre electrode pad and described second lead is connected to described peripheral electrode pad; And

The protectiveness packaging body is used to seal described semiconductor chip, and described first and described second lead, and described electrical connection,

It is characterized in that, described a plurality of first lead comprises alignment keys, when described semiconductor chip mounts to described first lead and when described first when being connected with described electrode pad by described electrical connection with described second lead, this alignment keys is used for described lead frame is aimed at described semiconductor chip.

16. semiconductor chip as claimed in claim 15 is characterized in that, described lead frame comprises connecting rod, and this connecting rod is connected on the siding track of lead-in wire moulding, and is sealed by described packaging body, and this lead-in wire moulding comprises described lead frame.

17. semiconductor die package as claimed in claim 15 is characterized in that, described first lead has tilting zone.

18. semiconductor die package as claimed in claim 15 is characterized in that, mounts to the described active surface of described semiconductor chip by described first lead of an electric insulation adhesive.

19. semiconductor die package as claimed in claim 18 is characterized in that, described first lead has the size of tilting zone and described tilting zone and is determined by the thickness of described semiconductor chip and the thickness of described adhesive.

20. semiconductor die package as claimed in claim 15 is characterized in that, described first lead comprises the bus bars that is used to connect power supply lead wire, is provided in the described semiconductor chip by this power supply lead wire stabilized power source voltage signal.

21. semiconductor die package as claimed in claim 15, it is characterized in that, described semiconductor chip has a plurality of safety boxs, they are formed on the described active surface, described safety box with the metal wire that can be exposed by laser cutting is used for replacing with good unit the trouble unit of described semiconductor chip, and wherein, described first lead directly mounts to described active surface and does not but cover described safety box.

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