Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
  • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
  • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04H—BROADCAST COMMUNICATION
  • H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
  • H04H60/02—Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linking to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
  • H04H60/04—Studio equipment; Interconnection of studios

Definitions

• the invention relates to a switching matrix for digital audio signals, which are supplied in parallel to the switching network inputs in individual sampling clock sequences with differing sampling frequencies in parallel representation via incoming data buses and are transmitted to any outgoing data buses of the same type in the same parallel representation via any switching field outputs that can be switched are, a separate switching matrix sampling clock being provided for the switching operations within the switching matrix.
• US Pat. No. 3,868,481 describes a time-division multiplex switching system (switching matrix) for digital signals, which works at different bit rates, which are distinguished by different word lengths (6 or 8 bits per byte) and different combinations of channels (or words) to 6, 12 or 24 channels per frame.
• the sampling rate is at this System is the same for all channels, which is the natural prerequisite for the fact that these channels can be combined to form a superordinate channel (highway).
• the incoming signals are converted by input units to a uniform byte and frame format, which is then offered to the switching matrix.
• the sampling rate of the outgoing signals is synchronous with the coupler clock multiplied by a rational factor. This must be selected accordingly in order to combine the To be able to convey 8 kHz sampled signals. Small frequency differences lead to periodic data loss, which is compensated for by resetting buffer memories (elastic buffers). For signals with strongly differing input sampling frequencies, as is the case with the invention
• the invention has set itself the task of producing the switching of audio signals with different sampling rates with the help of a single switching matrix with minimal effort. According to the invention, this is achieved in that, in order to achieve a match of the sampling clock sequences at the switching network outputs with those at the respectively assigned switching network inputs, the switching network sampling clock has a sampling frequency which is greater than all individual sampling frequencies and, on the one hand, at the switching network -Inputs each have an input buffer chain, each with an associated clock comparison circuit for obtaining an interference signal, which is a measure of the phase or frequency difference between the individual sampling frequency and the switching matrix sampling frequency, the interference signals during the transmission switching field sampling periods which are not required for audio data and which result from the switching field sampling frequency increased compared to all individual sampling frequencies are transmitted in coded form and that, on the other hand, one of the switching field outputs is transmitted Recovery of the respective individual sampling frequency is provided, depending on the assigned interference signal, controlled clock regeneration circuit, each with an assigned output buffer chain, and that the interference signals from the clock comparison circuits at the associated switching matrix input
• the switching principle used in the circuit according to the invention makes it necessary to temporarily store all the data (including the interference signals) originating from the inputs and synchronized with the switching matrix sampling frequency during a switching matrix sampling period, and the switching matrix outputs in the same time interval to be supplied with the corresponding data.
• this is achieved in that the storage locations provided for the temporary storage of the data within the switching matrix are assigned to one another as storage location pairs, the storage locations of which are alternately occupied with the data of successive sampling periods, such that in the a memory location of a memory location pair the data of the current scanning period are written in, while at the same time the data of the previous scanning period are read out from the other allocated memory location.
• the functions of the two memory locations are interchanged, so that the continuity of input and output is preserved and, furthermore, a time saving of 50% or a saving compared to an embodiment with a single memory location doubling of the possible number of channels can be achieved with the same switching matrix sampling period.
• FIG. 1 of the drawing shows the structure of one of the circuits provided at the switching matrix inputs.
• FIG. 3 shows the structure of one of the circuits provided at the switching network outputs.
• the switching matrix network KF is used to establish any connections between one of the switching matrix inputs and one of the switching field outputs. Of these, only two inputs and two outputs are shown in FIG. 1.
• the input signals are from analog-digital converters (not shown in the drawing), for example, via 20-bit input data buses EDI, ED2 ... each with an individual sampling frequency f. ,, ⁇ i 2 * '* ⁇ n para H e LDAR position supplied binary coded.
• the input data buses EDI, ED2 as well as the output data buses AD1, AD2 ... are each represented by a strongly drawn and a weakly drawn line.
• the strongly drawn lines symbolize the line bundle transmitting the coded data
• the weakly drawn lines each represent a single line, via which the sampling clock responsible for the coded data with the individual sampling frequencies f. ,, f- 2 to the shown two first inputs is transmitted.
• Data originating from any other inputs are transmitted by the switching matrix network KF with their individual sampling frequencies f 1. ,,? l __2 a ⁇ from the first two outputs.
• the numerical indices in the designations for the sampling frequencies only refer to the numbers of the inputs and outputs.
• the apostrophes f. say that the frequencies in question are picked up at the outputs.
• a centrally controlled common switching of all input signals takes place within the switching network, which would not be possible while maintaining the individual sampling frequencies f i - of the individual input signals. Accordingly, the input signals of their individual sampling frequencies f. " ⁇ I ? ' * - converted to the same coded signals, which have a switching matrix scanning frequency f. which is uniform for the entire switching matrix KF. At the switching network outputs, the signals transmitted via switching network KF are converted back to the original sampling frequencies' j i » f 'i2 * ' *.
• the memory locations of which are alternately occupied with the data of the successive scanning periods there are memories designed as memory location pairs, the memory locations of which are alternately occupied with the data of the successive scanning periods.
• the procedure for the assignments is such that the data of the current sampling period are written into the one memory location of a pair of memory locations, while at the same time the data of the previous sampling period are read out from the other allocated memory location. During the next sampling period, the functions of the two memory locations change.
• each switching matrix input there is one input buffer memory chain E1, E2 ..., to which a clock comparison circuit VI, V2 ... is assigned.
• Each of the input buffer chains has three digital memories. For each of the sampling clocks arriving at the individual frequency f. ,, f. "..., the associated data information is stored in the first memory. At the same time, the individual sampling clock f. ,, f i2 --- is compared in the 9 ⁇ eten clock comparison circuit VI, V2 ...
• a third buffer serves, as will be explained later with reference to FIG. 2, for inserting the interference signals, which are also shown in binary-coded form, into the data stream.
• each data stream conveyed from a switching matrix input to a switching matrix output additionally contains information about the individual sampling frequency of the input signal, which is passed via additional transmission cycles, in the form of the frequency difference and / or phase position of the individual sampling clock fl .l ,, 'f ⁇ .2 ... relative to the switching network sampling clock f .. Interfering signals II, 12 .... which provide information.
• the interference signal II, 12 ... which originates from the respectively connected input signals, is decoupled from the data flows and is used to regenerate the associated individual sampling clock of the input signal.
• One output buffer memory chain AI, A2 ... together with a clock regeneration circuit R1, R2 ... are provided.
• the data stream coming from the respective connected switching matrix input is, as will be explained in detail later with reference to FIG. 4, written into a first buffer with the switching matrix sampling frequency f ".
• the associated clock regeneration circuit R1, R2 ... which is provided with a controllable pulse generator which uses the interference signal to generate the corresponding individual Sampling frequency f ' j it f'. 2 ... is set, on the one hand, the useful information is read out of the last buffer of the output buffer chain AI, A2 and fed into the associated output data bus AD1, AD2 ...
• FIG. 2 shows the special configuration of a buffer memory chain E provided at a switching matrix input together with the associated clock comparison circuit V, which are each surrounded by dashed lines.
• the input signal offered via the incoming input data bus ED is generated with the individual sampling clock f . written into a first buffer ZI of the input buffer chain E.
• the individual sampling clock f. fed to the clock comparison device V, in which a bistable flip-flop K with its clear input L from the pulses of the sampling clock f. is applied.
• the clock comparison device V is further supplied with the pulses generated by the clock generator TG with the switching network sampling frequency f., And with this frequency f.,
• the set inputs SI and S2 of the flip-flop K and a memory stage SP are also applied.
• the memory stage SP also has a second set input S3, which is connected to the output of the flip-flop K.
• the memory stage SP is only set when a signal is present both at the set input S2 and at the set input S3, ie when a sampling pulse from the clock generator TG arrives and the flip-flop K is set at the same time.
• the outputs of the flip-flop K and the memory stage SP are connected to the inputs of an AND gate G, the output of which leads to a time counter ZW which is active for the duration of an output pulse of the gate G and has binary-coded time signals at its output ⁇ finished, whose quantization frequencies are independent of the coupling field sampling frequency and which originate from local quartz generators of the same frequency.
• U denotes a switching device which is controlled as a function of the output signal of the memory stage SP and which, when actuated, controls the data flow from the second buffer store Z2 to a third buffer store Z3 interrupts and connects the input of the buffer Z3 with the output of the time counter ZW.
• the switching matrix sampling frequency f .. is greater than each of the individual sampling frequencies f. Requires that for each of these individual sampling frequencies f. an integer n of sample periods arriving at the input with the period f. ⁇ there, whose total duration is approximately equal to the total duration of a number of (n + 1) switching matrix sampling periods, each with a period duration f ⁇ .
• the "coincidence" of a switching matrix sampling period with an input sampling period is always the case that a switching matrix sampling period lies entirely within an input sampling period.
• the first diagram, labeled "a” in FIG. 3 shows the input sampling pulses with the frequency f .; in the time interval between two successive sampling pulses, the respective current data word is present on the incoming input data bus ED. Some of these data words are symbolized by the names D0 ... D5. So these are with the frequency f. retrieved from the input data bus ED and stored in the first buffer ZI.
• the second diagram, labeled “b”, shows the pulses generated by the clock generator TG with the coupling field sampling frequency f.,. With this frequency f, the data DO ... written in the first buffer ZI are read out and written into the second buffer Z2. This results in the shift in the presence of the data DO ... in the intermediate memories ZI and Z2, which can be seen from the comparison of the diagrams a and b.
• the flip-flop K With each switching matrix scanning pulse (f), the flip-flop K is set via its set input SI and with each subsequent input scanning pulse (f.), The flip-flop K is reset via the clearing input L.
• the pulse diagram "c" resulting at the output of the flip-flop K is shown as the third in FIG. 3. As long as the pulses with the individual sampling frequency f i and the pulses with the switching matrix sampling frequency f. Arrive in alternating order, there is no output signal of the flip-flop K which lasts for a sampling period, since it is set with every switching matrix sampling pulse, but within each Sampling period is reset.
• the time counter ZW is connected to the input of the third buffer store Z3, which, as already mentioned, during the coincidence time of the output signals of the flip-flop K and the memory stage SP (shown in diagram "e” in FIG 3) supplies an interference signal which characterizes the duration of the coincidence time and which remains applied to the buffer Z3 at its input during the duration of the connection of the time counter ZW and thus to each sampling cycle during the last period of the number of inputs compared to the number of inputs gangs-scanning periods increased by one scanning periods of the Kopeldelfeld the difference time between the two scanning pulse sequences f. and f .. by means of the interference signal to the assigned switching network output.
• the scan sequence thus established is shown in FIG. 3 in diagram "f", in which the scan interval used to transmit the interference signal is designated Tx.
• FIG. 4 shows the circuit for a switching matrix output.
• This circuit consists of an output buffer chain A and a clock regeneration circuit R.
• the data arriving via the switching matrix are read into a first buffer memory Z'l in time with the switching field sampling frequency f ⁇ , the output of which is switched over by a switching device U 1 the data transmission is connected to a second buffer memory Z'2, which acts as a buffer memory.
• the switching device U ' is actuated by means of the signal si obtained from the buffer store Z'l in such a way that it switches the output of the buffer store Z'l to the input of one in the clock regeneration circuit R located Time counter ZZ connects, which is activated by a switching matrix sampling pulse, which decodes the data word present during the sampling interval Tx relating to the respective interference signal and sends a corresponding signal to a control device RE for a frequency f.
• adjustable pulse generator IG delivers. Since the pulse generator by the interference signal both frequency information about the input sampling frequency f.
• ST denotes a control circuit for the buffer memory Z'2, which converts the data supplied with the switching matrix sampling frequency f ⁇ from the buffer memory Z'l into data which is reconstructed with the individual sampling frequency f. Tobe offered. Finally, the reconstructed data are output to the output data bus AD via a further intermediate memory Z'3.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
• Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
• Television Receiver Circuits (AREA)
• Amplifiers (AREA)
• Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
• Stereo-Broadcasting Methods (AREA)

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• 1988
  • 1988-05-11 AT AT0123488A patent/AT389407B/de not_active IP Right Cessation
• 1989
  • 1989-05-11 EP EP89108529A patent/EP0342530B1/de not_active Expired - Lifetime
  • 1989-05-11 DE DE8989108529T patent/DE58900718D1/de not_active Expired - Fee Related
  • 1989-05-11 US US07/457,813 patent/US5099234A/en not_active Expired - Fee Related
  • 1989-05-11 EP EP89905676A patent/EP0374220A1/de active Pending
  • 1989-05-11 WO PCT/EP1989/000515 patent/WO1989011188A1/de not_active Ceased
  • 1989-05-11 AT AT89108529T patent/ATE71785T1/de active
• 1990
  • 1990-01-11 DK DK007990A patent/DK7990A/da not_active Application Discontinuation

Non-Patent Citations (1)

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