EP0459446A1 - Digital gesteuerter Oszillator - Google Patents

Digital gesteuerter Oszillator Download PDF

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Publication number
EP0459446A1
EP0459446A1 EP91108802A EP91108802A EP0459446A1 EP 0459446 A1 EP0459446 A1 EP 0459446A1 EP 91108802 A EP91108802 A EP 91108802A EP 91108802 A EP91108802 A EP 91108802A EP 0459446 A1 EP0459446 A1 EP 0459446A1
Authority
EP
European Patent Office
Prior art keywords
frequency
value
accumulation means
depending
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91108802A
Other languages
English (en)
French (fr)
Other versions
EP0459446B1 (de
Inventor
Katsuya Hori
Biichiro Mornaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of EP0459446A1 publication Critical patent/EP0459446A1/de
Application granted granted Critical
Publication of EP0459446B1 publication Critical patent/EP0459446B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator

Definitions

  • the present invention relates to a numerical control type oscillator whose oscillation frequency is controlled depending on set data.
  • a numerical control type oscillator is an oscillator whose oscillation frequency is controlled depending on set data. Such a numerical control type oscillator is used to provide a signal synchronized with a carrier wave of a signal sent from a communication satellite, for example.
  • an electric wave from the communication satellite is received at an antenna 41.
  • the carrier frequency of the signal sent from the communication satellite may by varied due to the Doppler effect.
  • the reception signal is converted into a predetermined frequency at a converter 42 which is provided near the antenna 41.
  • the signal from the converter 42 is supplied to a down-converter 43.
  • the signal is converted into an intermediate frequency signal with a predetermined frequency of several MHz at the down-converter 43.
  • the output of the down-converter 43 is supplied to a phase comparator 44.
  • the output of a numerical control type oscillator 45 is also fed to the phase comparator 44.
  • a phase comparison of the carrier wave from the down-converter 43 and the output of the numerical control type oscillator 45 is made at the phase comparator 44.
  • the phase comparison output is given to an A/D converter 47 through a low-pass filter 46.
  • the output of the A/D converter 47 is supplied to the numerical control type oscillator 45.
  • the oscillation frequency of the numerical control type oscillator 45 is controlled depending upon the output data of the A/D converter 47.
  • a signal synchronized with the carrier frequency can be provided from the numerical control type oscillator 45.
  • Fig. 2 shows a structure of a conventional numerical control type oscillator used for such a PLL circuit.
  • reference numeral 51 is a controller for setting a frequency.
  • a frequency setting value N depending on the output data of the A/D converter 47 is given to the controller 51.
  • the frequency setting value N is fed to a frequency setting register 52.
  • the output of the frequency register 52 is supplied to an adder 53.
  • the output of the adder 53 is given to an address register 54.
  • the output of the address register 54 is supplied to the adder 53.
  • a clock of a frequency F c is given to the address register 54 from a clock generator 55.
  • the output of the frequency setting register 52 is sequentially accumulated at the adder 53 and the address register 54.
  • the output of the address register 54 is supplied to an address of a waveform generating ROM 56.
  • Waveform data of one period is stored for an address of 2 i , for example, at the waveform generating ROM 56.
  • the waveform data is produced from the waveform generating ROM 56 according to an address from the address register 54.
  • the output of the waveform generating ROM 56 is supplied to a D/A converter 57.
  • the waveform data from the waveform shaping ROM 56 is converted into an analog waveform.
  • the analog waveform is taken out of an output terminal 58.
  • the circuit size increases correspondingly.
  • an object of the invention to provide a numerical control type oscillator capable of improving the frequency accuracy without increasing the circuit size.
  • a numerical control type oscillator whose output oscillation frequency is controlled depending on input numerical data, comprising: first accumulation means for accumulating a first set value which is set depending on the input numerical data with a first frequency and sequentially outputting the accumulated value; second accumulation means for accumulating a second set value which is set depending on the input numerical data with a second frequency and varying the first set value by a predetermined value temporarily when the accumulated value reaches a predetermined maximum value; and frequency generation means for outputting a frequency depending on an output of the first accumulation means as an oscillation frequency.
  • a controller is provided to execute the process for accumulating a second frequency setting value L and changing a first frequency setting value N to (N + 1) temporarily when the accumulated value B becomes a predetermined value B max .
  • Fig. 3 shows one embodiment of the invention.
  • reference numeral 1 is a controller for setting a frequency.
  • Frequency setting values N and L depending on the phase error component are given to the controller 1.
  • the frequency setting value N is for setting a main oscillation frequency.
  • the frequency setting value L is for setting a highly accurate frequency.
  • the frequency setting value N is supplied to a frequency setting register 2.
  • a control program is provided at the controller 1 so that the frequency setting value L is accumulated with the supply of an interrupt signal from an M-frequency divider 9 and that as soon as the accumulated value B becomes a predetermined value B max , the frequency setting value N, for example, is set at (N + 1).
  • a clock of a frequency F C is generated from a clock generator 5.
  • the clock is given to an interrupt terminal of the controller 1 through the M-frequency divider 9.
  • the controller 1 executes an interrupt processing as shown in Fig. 4.
  • the frequency setting value L is added with an accumulated value B to provide a new accumulated value B (step 11).
  • the accumulated value B is set at 0 in the initial state.
  • the frequency setting value set at the frequency setting register 2 is brought to N, and control is returned to a normal processing routine.
  • the maximum value B max is subtracted from the accumulated value B, the value (B - B max ) is brought to a new accumulated value B (step 14).
  • Fig. 3 the output of the frequency register 2 is given to an adder 3.
  • the output of the adder 3 is supplied to an address register 4.
  • the output of the address register 4 is fed to the adder 3.
  • the output of the address register 4 is given to an address of a waveform generating ROM 6. Data of one period is stored for an address of 2 i , for example, at the waveform generating ROM 6.
  • Waveform data is output from the waveform generating ROM 6 according to an address from the address register 4.
  • the output of the waveform generating ROM 6 is supplied to a D/A converter 7.
  • the waveform data from the waveform generating ROM 6 is converted into an analog waveform at the D/A converter 7.
  • the analog waveform is produced from an output terminal 8.
  • the controller 1 is provided to have a program for accumulating the frequency setting value L every output from the M-frequency divider 9 and bringing the frequency setting value to (N + 1) temporarily when the accumulated value B reaches the predetermined value B max . Therefore, frequencies between N and (N + 1) can be expressed, so that the frequency accuracy can be enhanced.
  • an address A k generated from the address register 4 is advanced every frequency setting value N with the clock F c by the adder 3 and the address register 4. Also, each time the accumulated value B of the frequency setting value L reaches the predetermined value B max , the frequency setting value N is set at (N + 1) temporarily.
  • the controller is provided to execute the processing for accumulating the second frequency setting value L and changing the first frequency setting value N to (N + 1) temporarily when the accumulated value B reaches the predetermined value B max . Consequently, the frequency accuracy of (1/B max ) can be obtained as compared with the conventional one, and the frequency accuracy can be enhanced without increasing the circuit size.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
EP91108802A 1990-05-31 1991-05-29 Digital gesteuerter Oszillator Expired - Lifetime EP0459446B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2143087A JPH0437205A (ja) 1990-05-31 1990-05-31 発振装置
JP143087/90 1990-05-31

Publications (2)

Publication Number Publication Date
EP0459446A1 true EP0459446A1 (de) 1991-12-04
EP0459446B1 EP0459446B1 (de) 1996-09-04

Family

ID=15330611

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91108802A Expired - Lifetime EP0459446B1 (de) 1990-05-31 1991-05-29 Digital gesteuerter Oszillator

Country Status (4)

Country Link
US (1) US5153526A (de)
EP (1) EP0459446B1 (de)
JP (1) JPH0437205A (de)
DE (1) DE69121777T2 (de)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0493057A1 (de) * 1990-12-20 1992-07-01 Motorola, Inc. Synthetisierer mit höherer Frequenzauflösung
EP0492588A3 (en) * 1990-12-26 1992-11-25 Hughes Aircraft Company Phase-locked loop frequency tracking device including a direct digital synthesizer
EP0604381A3 (de) * 1992-12-22 1994-07-27 Hughes Aircraft Company FSK-Modulator, der eine nicht ganzzahlige Anzahl von Abtastwerten in jedem Symbolraum benutzt
WO1994026033A1 (en) * 1993-05-03 1994-11-10 Nokia Telecommunications Oy Numerically controlled oscillator and digital phase locked loop
EP0660560A1 (de) * 1993-12-25 1995-06-28 Nec Corporation Taktregenerierungsverfahren und -schaltung
EP1215558A3 (de) * 2000-12-14 2005-03-30 NEC Electronics Corporation Verfahren und Schaltung zur Berechnung eines Vielfaches eines Einheitswertes und zum Erzeugen einer periodischen Funktion
EP1550934A1 (de) * 2003-12-29 2005-07-06 Teradyne, Inc. Mehrstufiger numerisch gesteuerter Oszillator

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365182A (en) * 1993-06-22 1994-11-15 Motorola, Inc. Method and apparatus for low power clock generation for high speed applications
CA2125113A1 (en) * 1993-08-31 1995-03-01 Francesco Ledda Method and circuitry for aligning the phase of high-speed clocks in telecommunications systems
US7002475B2 (en) * 1997-12-31 2006-02-21 Intermec Ip Corp. Combination radio frequency identification transponder (RFID tag) and magnetic electronic article surveillance (EAS) tag
US6167102A (en) * 1998-08-03 2000-12-26 Telefonaktiebolaget Lm Ericsson (Publ) System and method employing a reduced NCO lookup table
FR2832271A1 (fr) * 2001-11-13 2003-05-16 Koninkl Philips Electronics Nv Tuner comprenant un convertisseur de tension

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3824498A (en) * 1972-12-22 1974-07-16 Dallas Instr Inc Digital processor for selectively synthesizing sinusoidal waveforms and frequency modulations
EP0312370A2 (de) * 1987-10-13 1989-04-19 Matsushita Electric Industrial Co., Ltd. Digitaloszillator

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3973209A (en) * 1975-08-29 1976-08-03 Rca Corporation Digital arithmetic synthesizer phase lock loop with direct doppler and frequency readout
US4652832A (en) * 1985-07-05 1987-03-24 Motorola, Inc. Frequency resolution in a digital oscillator
US4901265A (en) * 1987-12-14 1990-02-13 Qualcomm, Inc. Pseudorandom dither for frequency synthesis noise

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3824498A (en) * 1972-12-22 1974-07-16 Dallas Instr Inc Digital processor for selectively synthesizing sinusoidal waveforms and frequency modulations
EP0312370A2 (de) * 1987-10-13 1989-04-19 Matsushita Electric Industrial Co., Ltd. Digitaloszillator

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 6, no. 185 (E-132)(1063) September 21, 1982 & JP-A-57 99 007 (FUJITSU K.K. ) June 19, 1982 *
RESEARCH DISCLOSURE no. 316, August 1990, EMSWORTH page 646; TRAN THONG: 'INCREASED FREQUENCY RESOLUTION DIGITAL SIGNAL GENERATOR ' *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0493057A1 (de) * 1990-12-20 1992-07-01 Motorola, Inc. Synthetisierer mit höherer Frequenzauflösung
US5495505A (en) * 1990-12-20 1996-02-27 Motorola, Inc. Increased frequency resolution in a synthesizer
EP0492588A3 (en) * 1990-12-26 1992-11-25 Hughes Aircraft Company Phase-locked loop frequency tracking device including a direct digital synthesizer
EP0604381A3 (de) * 1992-12-22 1994-07-27 Hughes Aircraft Company FSK-Modulator, der eine nicht ganzzahlige Anzahl von Abtastwerten in jedem Symbolraum benutzt
WO1994026033A1 (en) * 1993-05-03 1994-11-10 Nokia Telecommunications Oy Numerically controlled oscillator and digital phase locked loop
AU678465B2 (en) * 1993-05-03 1997-05-29 Nokia Telecommunications Oy Numerically controlled oscillator and digital phase locked loop
EP0660560A1 (de) * 1993-12-25 1995-06-28 Nec Corporation Taktregenerierungsverfahren und -schaltung
US5546032A (en) * 1993-12-25 1996-08-13 Nec Corporation Clock signal regeneration method and apparatus
EP1215558A3 (de) * 2000-12-14 2005-03-30 NEC Electronics Corporation Verfahren und Schaltung zur Berechnung eines Vielfaches eines Einheitswertes und zum Erzeugen einer periodischen Funktion
US7069283B2 (en) 2000-12-14 2006-06-27 Nec Electronics Corporation Method and circuit for calculating multiple of unit value and generating a periodic function
EP1550934A1 (de) * 2003-12-29 2005-07-06 Teradyne, Inc. Mehrstufiger numerisch gesteuerter Oszillator
US7064616B2 (en) 2003-12-29 2006-06-20 Teradyne, Inc. Multi-stage numeric counter oscillator

Also Published As

Publication number Publication date
JPH0437205A (ja) 1992-02-07
EP0459446B1 (de) 1996-09-04
DE69121777T2 (de) 1997-01-16
US5153526A (en) 1992-10-06
DE69121777D1 (de) 1996-10-10

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