EP1454405B1 - Geregelte frequenzleistungsfaktorkorrekturschaltung und verfahren - Google Patents

Geregelte frequenzleistungsfaktorkorrekturschaltung und verfahren Download PDF

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Publication number
EP1454405B1
EP1454405B1 EP01988294A EP01988294A EP1454405B1 EP 1454405 B1 EP1454405 B1 EP 1454405B1 EP 01988294 A EP01988294 A EP 01988294A EP 01988294 A EP01988294 A EP 01988294A EP 1454405 B1 EP1454405 B1 EP 1454405B1
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Prior art keywords
coil
current
signal
input
clock
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French (fr)
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EP1454405A1 (de
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Joel Turchi
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Definitions

  • the present invention relates in general to integrated circuits and, more particularly, to integrated power factor correction circuits.
  • Integrated power factor correction (PFC) circuits are switching circuits that ensure that an alternating current (AC) line is loaded with an in-phase, substantially sinusoidal current.
  • PFC alternating current
  • many electrical systems draw current from the AC line voltage only near the peak voltage levels of the AC line.
  • the aggregate effect of loading the AC line with large currents at the voltage peaks and zero current at other times is to produce distortion of the AC line voltage.
  • systems without PFC can cause high neutral currents to flow in three-phase distribution networks.
  • the distribution networks of regional utility companies must be oversized, which necessitates a large capital investment.
  • Several governments are mandating that PFC be incorporated in the power supplies used in some or all electrical devices.
  • PFC circuits typically switch current through an inductor or coil from the AC line at a frequency much higher than the frequency of the AC line to magnetize or charge a coil.
  • systems may use a switching frequency of at least one hundred kilohertz when the AC line frequency is fifty hertz.
  • the energy stored in the coil is discharged into a capacitor to generate an intermediate PFC direct current (DC) supply voltage to power an electrical device or system.
  • DC direct current
  • the average value over a switching period of the current switched through the coil is made proportional to the current voltage on the AC line. The result is a high effective power factor for the AC line.
  • Previous PFC circuits operate in a free-running mode in which a current is switched to charge the coil as soon as the coil current stored in the previous cycle has been discharged across the capacitor.
  • the previous PFC circuits switch at a frequency that varies with the current AC line voltage as well as the system's load current.
  • Such variable switching frequencies are difficult to filter out in order to suppress or remove electromagnetic interference generated by the switched coil currents.
  • Such filtering requires complex filters which dissipate power and substantially increase the manufacturing cost of a system.
  • One known PFC circuit is the UC3854 High Power Factor Deregulator described in the Unitrode data sheet for this circuit.
  • the UC 3854 provides active power factor correction for power systems that otherwise would draw non-sinusoidal current from sinusoidal power lines. This device uses average current-mode control to accomplish fixed frequency current control with stability and low distortion.
  • FIG. 1 is a schematic diagram of a power factor correction (PFC) circuit
  • FIG. 2 is a timing diagram showing waveforms of the PFC circuit
  • FIG. 3 is a schematic diagram of a duty cycle sensor of the PFC circuit
  • FIG. 4 is a schematic diagram of a current modulator of the PFC circuit.
  • FIG. 5 is a schematic diagram of the current modulator in an alternate embodiment.
  • FIG. 1 is a schematic diagram of a power factor correction (PFC) circuit 100 controlled by a PFC control circuit 10 and including a diode bridge 20, resistors 22-24, an inductor or coil 25, a diode 26, an output capacitor 27, a timing capacitor 28 and a switching transistor 29.
  • PFC circuit 100 receives a sinusoidal voltage VAC from an alternating current (AC) line and produces a direct current (DC) PFC output signal V OUT at a node or output 30.
  • AC alternating current
  • DC direct current
  • PFC circuit 100 functions as a step up switching regulator that receives VAC at a value of about two hundred twenty volts root-mean-square (RMS) and a frequency of about fifty hertz and produces PFC output voltage V OUT with a value of about four hundred volts DC.
  • VAC has a value of about one hundred ten volts RMS and V OUT a frequency of sixty hertz.
  • VAC has a typical range of about plus and minus,twenty percent.
  • Diode bridge 20 is a standard full-wave bridge rectifier that rectifies line voltage VAC and produces a rectified sine wave voltage V IN at a node 32 with a frequency of twice the frequency of VAC or about one hundred hertz and a peak value of about three hundred ten volts.
  • a capacitor (not shown) may be connected across diode bridge 20 to reduce VAC noise peaks.
  • Transistor 29 is a high current n-channel metal-oxide-semiconductor field effect transistor that switches a coil current I COIL through coil 25.
  • transistor 29 is a power transistor able to switch peak values of coil current I COIL greater than two amperes. These currents are small near the zero crossing point of VAC and large near the VAC voltage peaks.
  • Transistor 29 typically has a large gate capacitance greater than five hundred picofarads.
  • Coil current I COIL has a component charging current I CH and a component discharging current I DSCH .
  • Charging current I CH flows through coil 25 to store magnetic energy in coil 25 when transistor 29 is on.
  • transistor 29 switches off, the stored magnetic energy flows as discharge current I DSCH from coil 25 through diode 26 to capacitor 27 to develop PFC voltage V OUT on node 30.
  • Coil current I COIL has a return path through resistor 22 to diode bridge 20 which develops a current sense voltage V IS on a node 31 to monitor when I COIL is flowing.
  • resistor 22 has a resistance of about 0.2 ohms, so V IS has a value of about -0.2 volts when I COIL has a magnitude of one ampere.
  • the conduction time of I COIL can be measured using a voltage sensing technique, rather than the current sensing arrangement shown in FIG. 1.
  • coil 25 can be formed as a primary winding of a transformer whose secondary winding has a terminal coupled at node 31 to the input of duty cycle sensor 12, typically through a resistor, the other secondary winding terminal being grounded. The secondary winding generates current sense voltage V IS with a positive voltage when I COIL is charging, a negative voltage while I COIL is discharging, and with substantially zero volts when I COIL is zero.
  • I COIL is a function of PFC output voltage V OUT , and is controlled by feeding back V OUT through a voltage divider formed with resistors 23 and 24. This voltage divider samples V OUT and provides a sense voltage V SENSE on a node 36. Resistors 23 and 24 have resistances of R 23 and R 24 , respectively.
  • PFC control circuit 10 includes a duty cycle sensor 12, a current modulator 14, a flip-flop or latch 16 and an output buffer 18.
  • Current modulator 14 produces a timing current I TIMING that charges an external capacitor 28 to develop a timing voltage V TIMING that controls the period of charging current I CH , and therefore its peak amplitude, as described below.
  • PFC control circuit 10 is formed on a semiconductor substrate as an integrated circuit.
  • Output buffer 18 is a standard non-inverting amplifier that is capable of driving the high capacitive load presented by transistor 29.
  • Latch 16 is a standard R-S flip-flop that has a Q output providing a digital switching signal VSW which is set on a transition edge of a clock signal CLOCK and reset on a transition edge of a digital termination signal TERM.
  • CLOCK preferably operates at a frequency much greater than the frequency of V IN .
  • V IN has a frequency of about one hundred hertz, or a period of about ten milliseconds
  • CLOCK pulses are generated at a controlled or substantially constant frequency of about one hundred kilohertz, or a period of about ten microseconds.
  • transistor 29 When VSW is set, transistor 29 turns on through output buffer 18 to initiate charging component I CH of coil current I COIL to magnetize or store energy in coil 25. When VSW is reset, transistor 29 is turned off through output buffer 18, terminating charging component I CH and initiating discharging component I DSCH of I COIL , which flows through diode 26 to transfer energy from coil 25 to capacitor 27.
  • Duty cycle sensor 12 monitors coil current I COIL and produces a digital coil current sense signal COILON at an output 34 which is logic high when I COIL has a substantially nonzero value and logic low when I COIL is zero.
  • a comparator compares current sense signal V IS with a reference signal V REF2 to generate COILON.
  • duty cycle sensor 12 includes a preamplifier that increases the magnitude of V IS to improve noise immunity. Since VSW is set on each CLOCK pulse to begin a new cycle, the portion of a CLOCK period in which COILON is logic high is indicative of the duty cycle of I COIL .
  • Current modulator 14 has an input at node 36 that monitors PFC signal V OUT through sense signal V SENSE to establish a time T CH for the charging portion I CH of coil current I COIL .
  • An input at node 34 senses when I COIL is flowing to provide a digital signal COILON that establishes a duty cycle of I COIL over a CLOCK period.
  • Current modulator 14 includes an error amplifier that amplifies the difference between V SENSE and a reference voltage V REF1 to produce a correction signal V ERR for setting the magnitude of I COIL , and therefore the time T CH .
  • TERM is produced as a function of T CH and the duty cycle. In one embodiment, TERM is produced so as to maintain a constant product of T CH and the duty cycle of I COIL .
  • Switching cycles of PFC control circuit 10 are initiated by clock signal CLOCK which preferably operates at a constant or nearly constant frequency. Since the period of CLOCK is much smaller than the period of V IN , a substantially constant voltage V IN appears across coil 25 when transistor 29 turns on.
  • FIG. 2 is a timing diagram showing selected waveforms of PFC control circuit 10.
  • clock signal CLOCK, switching signal VSW, termination signal TERM and coil current sense signal COILON are all low.
  • coil current I COIL , current sense voltage V IS , timing current I TIMING and timing voltage V TIMING each are equal to zero.
  • a low to high transition edge of CLOCK sets latch 16 to induce a low to high transition of VSW, turning on transistor 29 through buffer 18 to initiate coil current I COIL .
  • the component of I COIL that begins to flow at time T1 is charging current I CH . Since the period of CLOCK is much less than the period of V IN , and the voltage drop across transistor 29 typically is small, a substantially constant voltage V IN is applied across coil 25 to cause I COIL to increase linearly or ramp up at a rate V IN /L as shown.
  • I COIL flows through resistor 22 to develop current sense voltage V IS , which also ramps linearly but in a negative voltage direction as shown.
  • the low to high VSW transition sets COILON high to enable timing current I TIMING , which charges capacitor 28 to develop timing voltage V TIMING as a linear ramp.
  • V TIMING reaches a threshold voltage to generate a low to high transition of termination signal TERM, which resets latch 16.
  • This threshold voltage may be a predetermined voltage or a variable voltage, as described in detail below.
  • a high to low transition of VSW terminates charging current I CH and initiates discharging current I DSCH of I COIL to transfer energy from coil 25 to capacitor 27.
  • VSW also closes a switch that discharges capacitor 28 and shunts I TIMING to ground to reduce V TIMTNG to zero as shown.
  • I DSCH decreases in a linear fashion with a slope (V OUT -V IN )/L until the magnetic energy stored in coil 25 is fully discharged.
  • I COIL decreases to zero.
  • Current sense signal V IS also ramps to zero, which produces a high to low transition of coil current sense signal COILON.
  • I COIL remains substantially zero for the remainder of the CLOCK period until time T4, when the next cycle begins.
  • FIG. 3 shows a schematic diagram of duty cycle sensor 12 coupled to resistor 42, including an amplifier 44, a comparator 45, a latch 46 and resistors 42-43.
  • Duty cycle sensor 12 receives sense signal V IS at node 31 through resistor 42 to monitor the flow of coil current I COIL .
  • An output is coupled to node 34 to produce coil current sense signal COILON with a logic low value when I COIL is substantially zero and a logic high value when I COIL is nonzero.
  • a logic low to high transition of clock signal CLOCK sets switching signal VSW to a logic high value to initiate coil current I COIL .
  • Latch 46 is set to produce a low to high logic transition of COILON on node 34 to indicate that I COIL is flowing, i.e., has a nonzero value.
  • sense signal V IS ramps from zero to a negative value.
  • Amplifier 44 and resistors 42-43 function as a gain stage that amplifies V IS to increase the system noise immunity.
  • resistor 43 has a value of about ten kilohms and resistor 42 has a value of about one kilohm, which results in an amplified signal on a node 41 whose value is about (-10*V IS ).
  • node 41 ramps from zero to a positive level until time T2, when its value begins to decrease toward zero volts as coil 25 discharges.
  • V REF2 When the potential on node 41 decreases to a value less than V REF2 , comparator 45 generates a logic low to high transition of a reset signal V R , which resets latch 46 to produce a high to low logic transition of COILON that indicates that I COIL has discharged to substantially zero.
  • V REF2 may be set to a small positive nonzero value to avoid an oscillatory condition in comparator 45 that effectively introduces noise in V R .
  • FIG. 4 is a schematic diagram showing current modulator 14 in further detail, including amplifiers 47-48, a comparator 49, switches 50-51, resistors 52-53, capacitors 54-55 and a current source 56.
  • Resistors 52 and 53 have resistances R 52 and R 53 , respectively, while capacitors 54 and 55 have capacitances C 54 and C 55 , respectively.
  • PFC control circuit 10 effectively regulates VOUT by maintaining VSENSE substantially equal to VREF1.
  • Capacitor 54 and resistors 23-24 function as an integrator or low pass filter which filters out either one hundred hertz or one hundred twenty hertz ripple in V SENSE which may be present in PFC signal V OUT , depending on the local or regional frequency of VAC.
  • Capacitor 54 and resistors 23-24 produce an integration time constant R 23 *R 24 *C 54 /(R 23 +R 24 ) that attenuates V SENSE fluctuations having a shorter duration.
  • the time constant is at least five times the period of V IN so, for example, when V IN has a period of ten milliseconds, the time constant is set to be at least fifty milliseconds.
  • V ERR is considered to be substantially constant over a period of V IN .
  • Correction signal V ERR is effectively divided by the duty cycle of I COIL in a gain stage 70 that includes amplifier 48, resistors 52-53, capacitor 55 and switch 50.
  • Gain stage 70 functions as an integrator whose time constant is set by resistors 52-53 and capacitor 55 to filter out switching transients present when switch 50 is opened and closed at the frequency of clock signal CLOCK.
  • This time constant preferably has a value in the range of five times the period of CLOCK or greater. For example, if a period of CLOCK is ten microseconds, the time constant of resistors 52-53 and capacitor 55 preferably is at least fifty microseconds.
  • a control or threshold signal V TON is provided at a node 74.
  • gain stage 70 The operation of gain stage 70 is as follows.
  • COILON is high, such as from time T1 to time T3 (I COIL is nonzero)
  • switch 50 is open.
  • V ERR functions as a reference voltage coupled to the non-inverting input of amplifier 48.
  • COILON is low, such as from time T3 to T4 (I COIL is zero)
  • switch 50 is closed and the voltage across switch 50 is approximately zero. Substantially zero volts is then applied to the inverting input of amplifier 48 through resistor 52.
  • V TIMING is generated by charging a capacitance C 28 with a constant current I TIMING , and therefore has a ramp shape that is a linear function of I TIMING .
  • V TON is coupled to an input of comparator 49 to control the trip point at which timing voltage V TIMING sets termination signal TERM to logic high to terminate charging current I CH .
  • I TIMING is held substantially constant while correction voltage V ERR is adjusted by COILON to generate threshold voltage V TON so that the product T CH *D CYCLE is substantially constant.
  • V ERR correction voltage
  • V TON threshold voltage
  • the average value of I COIL is sinusoidal and in phase with AC line voltage VAC, which results in a high power factor.
  • the high power factor is achieved while switching coil current I COIL at a constant frequency with clock signal CLOCK to reduce the level of electromagnetic interference or to facilitate its attenuation by filtering.
  • FIG. 5 is a schematic diagram showing current modulator 14 in an alternate embodiment.
  • correction voltage V ERR is coupled directly to the inverting input of comparator 49 to control the switching threshold of V TIMING , while I TIMING is adjusted by duty cycle DC of I COIL to maintain the product T CH *D CYCLE constant.
  • the output of amplifier 60 controls the base current of a transistor 65 in conjunction with a resistor 69.
  • This arrangement produces a collector current I 65 which is subtracted from a reference current I REF2 to produce a current I OUT that develops a voltage V 67 across resistor 67.
  • I TIMING is proportional to duty cycle D CYCLE .

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Claims (11)

  1. Eine Blindstromkompensationsschaltung (100), mit:
    einer ersten Verriegelungsschaltung (16, 18) mit einem Ausgang (Q, VSW) zum Hervorrufen eines Spulenstroms (ICOIL) in einer Spule (25), als Antwort auf eine Übergangsflanke eines Taktsignals (CLOCK), um ein Blindstromkompensationssignal (VOUT, 30) zu generieren, und einem Eingang für das Empfangen eines Steuersignals (TERM, 38); und
    einer Strommodulationsschaltung (14), die einen ersten Eingang (VSENSE, 30), der für das Empfangen des Blindstromkompensationssignals (VOUT, 30) verschaltet ist, um eine Ladezeit des Spulenstroms festzulegen, einen zweiten Eingang (34), der für das Abtasten des Spulenstroms (ICOIL) verschaltet ist, um einen Einschaltzyklus des Spulenstroms über eine Periode (T4-T1) des Taktsignals (CLOCK) festzulegen, und einen Ausgang (38) zum Bereitstellen des Steuersignals (TERM) hat;
    dadurch gekennzeichnet, dass der Einschaltzyklus des Spulenstroms ein Anteil (T3-T1) einer Periode (T4-T1) des Zeitsignals (CLOCK) ist, währenddessen der Ladestrom und der Entladestrom beide im Wesentlichen nicht null sind, und, dass das Steuersignal eine Funktion von beiden, der Ladezeit (T2-T1) und dem Einschaltzyklus (T3-T1), ist.
  2. Die Blindstromkompensationsschaltung nach Anspruch 1, wobei die Strommodulationsschaltung (14) aufweist:
    einen ersten Verstärker (47), der einen ersten Eingang zum Empfang des Blindstromkompensationssignals (VOUT) und der einen zweiten Eingang zum Empfang eines Referenzsignals (VREF1) hat; und
    einen zweiten Verstärker (48), der einen ersten Eingang (72), der mit einem Ausgang (VERR) des ersten Verstärkers (47) verschaltet ist, und der einen Ausgang (74) zum Bereitstellen eines Steuersignals (TERM) hat.
  3. Die Blindstromkompensationsschaltung nach Anspruch 2, wobei
    die Strommodulationsschaltung (14) ferner einen ersten Schalter (50) aufweist, der als Antwort auf ein Tastsignal schaltet, das an dem zweiten Eingang (34) der Strommodulationsschaltung (14) angelegt ist, zum schalten eines zweiten Eingangs (73) des zweiten Verstärkers (48) von dem Ausgang des zweiten Verstärkers (48) auf einen Masseknoten, um einen Einschaltzyklus (T3-T1) festzulegen.
  4. Die Blindstromkompensationsschaltung nach Anspruch 1, ferner mit einem Stromsensor (22, 42; 12), der einen Eingang (39) zum Abtasten des Spulenstroms (ICOIL) verschaltet und einen Ausgang (34) zum Bereitstellen eines Tastsignals (COILON) hat.
  5. Die Blindstromkompensationsschaltung nach Anspruch 4, wobei der Stromsensor (12) aufweist:
    einen ersten Verstärker (44, 45), der einen ersten Eingang, der mit dem Eingang (39) des Stromsensors verschaltet ist, und einen zweiten Eingang zum Festlegen eines Schwellwertes (VREF2) des Spulenstroms (ICOIL) hat; und
    eine zweite Verriegelungsschaltung (46), die einen ersten Eingang, der mit dem Ausgang der ersten Verriegelungsschaltung (16) verschaltet ist, einen zweiten Eingang, der mit einem Ausgang des ersten Verstärkers (44, 45) verschaltet ist, und einen Ausgang (34) hat, der mit dem zweiten Eingang der Strommodulationsschaltung (14) verschaltet ist, zum Generieren des Tastsignals (COILON) als einen ersten logischen Zustand an der Übergangsflanke des Zeitsignals (CLOCK) und als einen zweiten logischen Zustand, wenn der Spulenstrom unter den Schwellwert (VREF2) fällt.
  6. Die Blindstromkompensationsschaltung nach Anspruch 5, wobei die Strommodulationsschaltung (14) aufweist:
    einen Vergleicher (49), der einen, zum Empfang eines Rampensignals (VTIMING) verschalteten Eingang, und der einen Ausgang (38), zum Bereitstellen eines Streusignals (TERM), hat;
    einen zweiten Verstärker (47), der einen ersten Eingang zum Empfangen des Blindstromkompensationssignals (VOUT; VSENSE), einen zweiten Eingang, zum Empfangen eines Referenzsignals (VREF1), und einen Ausgang (79) hat, der mit einem zweiten Eingang des Vergleichers (49) verschaltet ist; und
    eine Durchschnittsschaltung (50, 60, 64, 66), die einen Eingang, der mit dem Ausgang (34) der zweiten Verriegelungsschaltung (46) verschaltet ist, zur Durchschnittsberechnung eines ersten Referenzstroms (IREF1) über die Periode des Taktsignals (CLOCK) hat, um einen Durchschnittsstrom (I65) zu erzeugen, der beispielhaft für den Einschaltzyklus (T3-T1) ist.
  7. Die Blindstromkompensationsschaltung nach Anspruch 6, wobei die Durchschnittsschaltung aufweist:
    einen Schalter (50) zum Schalten des ersten Referenzsignals (IREF1) mit dem Tastsignal (COILON), um ein Einschaltzyklussignal (V66) zu erzeugen; und
    einen Integrator (60), der einen ersten Eingang zum Empfangen eines zweiten Referenzsignals (68), einen zweiten Eingang, zum Empfangen des Einschaltzyklussignals (V66), und einen Ausgang, zum Bereitstellen des Durchschnittsstroms (I65) hat.
  8. Ein Verfahren zum Kompensieren eines Blindstroms mit den Schritten:
    Hervorrufen eines Spulenstroms (ICOIL) an einer Spule zu Beginn einer Taktperiode, um ein blindstromkompensiertes Signal (VOUT, 30) zu erzeugen;
    dadurch gekennzeichnet, dass das Verfahren folgende Schritte aufweist:
    Tasten (22, 42, 12) des Spulenstroms (ICOIL), um einen Einschaltzyklus (T3-T1) des Spulenstroms über die Taktperiode zu ermitteln; und
    Auslöschen des Ladeanteils des Spulenstroms (ICOIL) mit einem Steuersignal (TERM), das eine Funktion von beiden, dem Blindstromkompensationssignal und dem Einschaltzyklus, ist, wobei der Einschaltzyklus des Spulenstroms ein Anteil (T3-T1) einer Periode (T4-T1) des Taktsignals (CLOCK) ist, während dem beide, der Ladestrom und der Entladestrom, im Wesentlichen nicht null sind.
  9. Das Verfahren nach Anspruch 8, wobei der Schritt des Auslöschens folgende Schritte aufweist:
    Verstärken (47) einer Differenz zwischen dem Blindstromkompensationssignal (VSENSE) und einem ersten Referenzsignal (VREF1) um ein Kompensationssignal (VERR) zu erzeugen; und
    Teilen des Kompensationssignals (VERR) durch den Einschaltzyklus (T3-T1), um das Steuersignal (TERM) zu erzeugen.
  10. Das Verfahren nach Anspruch 9, wobei der Schritt des Multiplizierens die folgenden Schritte aufweist:
    Zuleiten des Kompensationssignals (VERR) zu einem ersten Eingang (72) eines Verstärkers (48);
    Schalten (50) eines zweiten Eingangs (73) des Verstärkers (48) auf einen Ausgang des Verstärkers (48), während der Spulenstrom (ICOIL) fließt; und
    Schalten (50) des zweiten Eingangs (73) des Verstärkers (48) auf einen Masseknoten, wenn der Spulenstrom abbricht.
  11. Eine integrierte Blindstromkompensationsschaltung, mit:
    einer Steuerschaltung (16, 18), die einen ersten Eingang, zum Empfangen von Taktpulsen (CLOCK), um einen Spulenstrom (ICOIL) in einer Spule (25) hervorzurufen, einen zweiten Eingang (38), zum Empfangen eines Steuersignals (TERM), um einen Ladungsanteil (T2-T1) des Spulenstroms (ICOIL) auszulöschen, und einen Ausgang (VSW) hat, zum Generieren eines Blindstromkompensationssignals (VOUT) mit dem Spulenstrom (ICOIL); und
    einer Modulationsschaltung (14), die einen ersten Eingang (VSENSE, 36), der zum Tasten des Blindstromkompensationssignals (VOUT) verschaltet ist, um eine Amplitude des Spulenstroms (ICOIL) festzulegen, einen zweiten Eingang (34), zum Überwachen des Spulenstroms (ICOIL) über eine Periode von Taktpulsen (CLOCK), um ein Einschaltzyklussignal (V66) zu erzeugen, und einen Ausgang, zum Bereitstellen eines Steuersignals hat;
    dadurch gekennzeichnet, dass das Einschaltzyklussignal (V66) eine Funktion des Einschaltzyklus des Spulenstroms (ICOIL) ist, und wobei der Einschaltzyklus (T3-T1) des Spulenstroms (ICOIL) ein Anteil (T3-T1) einer Periode (T4-T1) des Zeitsignals ist, während der beide, ein Ladestrom und ein Entladestrom der Spule, im Wesentlichen nicht null sind, und, dass das Steuersignal eine Funktion von beiden, der Amplitude des Spulenstroms und dem Einschaltzyklussignal (V66), ist.
EP01988294A 2001-12-12 2001-12-12 Geregelte frequenzleistungsfaktorkorrekturschaltung und verfahren Expired - Lifetime EP1454405B1 (de)

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PCT/US2001/047725 WO2003050935A1 (en) 2001-12-12 2001-12-12 Controlled frequency power factor correction circuit and method

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DE60124789T2 (de) 2007-09-13
WO2003050935A1 (en) 2003-06-19
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TWI290413B (en) 2007-11-21
EP1454405A1 (de) 2004-09-08
ES2274910T3 (es) 2007-06-01

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