EP1979934B1 - Procede de traitement d'une plaquette semi-conductrice contenant de l'oxygene et composant semi-conducteur - Google Patents

Procede de traitement d'une plaquette semi-conductrice contenant de l'oxygene et composant semi-conducteur Download PDF

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EP1979934B1
EP1979934B1 EP07702904A EP07702904A EP1979934B1 EP 1979934 B1 EP1979934 B1 EP 1979934B1 EP 07702904 A EP07702904 A EP 07702904A EP 07702904 A EP07702904 A EP 07702904A EP 1979934 B1 EP1979934 B1 EP 1979934B1
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wafer
semiconductor
zone
region
irradiation
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EP1979934A1 (fr
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Hans-Joachim Schulze
Helmut Strack
Anton Mauder
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0289—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes

Definitions

  • the present invention relates to a method for treating an oxygen-containing semiconductor wafer.
  • CMOS single crystals for example silicon monocrystals
  • FZ method float zone method
  • CZ method Czochralski method
  • the CZ method is cheaper to carry out in comparison to the FZ method, but has the disadvantage that the single crystal has a high oxygen concentration due to the production method, which is typically in the range of a few 10 17 atoms / cm 3 .
  • oxygen precipitates oxygen precipitates.
  • These are to be understood as meaning oxygen agglomerates or oxygen vacancy agglomerates in the semiconductor crystal.
  • these precipitates act as gettering centers for heavy metal atoms, which can get into the wafer during the manufacturing process of the components. If such precipitates are present in an active device zone of a semiconductor device, however, they lead to a deterioration of the device properties, by acting as recombination centers for free charge carriers act and by acting as a generation centers for charge carrier pairs, the latter leads to an increase in the leakage current flowing in the blocking operation of the device.
  • CZ wafers have only limited suitability for the realization of power devices which have a dielectric strength of a few hundred volts without further treatment.
  • CZ wafers are suitable without further treatment for these components only as a semiconductor substrate, on which by means of complex and thus costly epitaxial method further (oxygen-poor) semiconductor layers are applied, in which the reverse voltage receiving areas of a power device, such as the drift region of a MOSFET or n- Basis of an IGBT, be realized.
  • One known method of preventing oxygen precipitates in near-surface regions of a wafer is to reduce the oxygen concentration in that region of the wafer by out-diffusing oxygen atoms from the near-surface region of the wafer by means of a temperature process.
  • the US Pat. No. 6,849,119 B2 (Falster ) describes a method in which a CZ semiconductor wafer is subjected to a temperature process in which the back side of the wafer is a nitriding atmosphere and the front side thereof is a non-nitriding one Atmosphere is exposed.
  • This temperature treatment leads to the generation of crystal vacancies, with the maximum of a self-adjusting vacancy profile being closer to the back than to the front.
  • the wafer is then subjected to another temperature treatment at temperatures of 800 ° C and 1000 ° C, whereby oxygen precipitates arise in areas of high vacancy concentration.
  • the EP 0769809 A1 (Schulze ) describes a method for reducing the vacancy concentration in a wafer by injecting interstitial silicon into the wafer as a result of an oxidation process.
  • the object of the present invention is to provide a method for treating an oxygen-containing wafer used for the production of semiconductor components by which oxygen precipitations in a near-surface region of the wafer are prevented and in which a pane region opposite the near-surface region preferably has a Zone is generated, which has a high density of oxygen precipitates.
  • An exemplary embodiment of the method according to the invention for treating a semiconductor wafer containing oxygen which has a first side, a second side opposite the first side, a first semiconductor region adjoining the first side, and a second semiconductor region adjoining the second side, provides To irradiate the second side of the wafer with high-energy particles, thereby crystal defects - such. B. vacancies, double vacancies or voids / oxygen complexes - to produce in the second semiconductor region of the wafer.
  • a first temperature process is performed in which the wafer is heated for a predetermined period of time to temperatures between 700 ° C and 1100 ° C.
  • the second semiconductor region which has a high concentration of crystal defects and thus a high concentration of crystal lattice vacancies in comparison to the first semiconductor region, e.g. B. higher valence vacancies (V) oxygen (O) complexes (eg, O 2 V complexes).
  • V valence vacancies
  • O oxygen
  • vacancy oxygen complexes act as nucleation nuclei, to which further oxygen atoms or oxygen ions or even further vacancies / oxygen complexes attach, resulting in stable oxygen agglomerates in the second semiconductor region.
  • the vacancy oxygen complexes or the oxygen agglomerates act as getter centers for impurities present in the semiconductor wafer, such as, for example, heavy metal atoms, and for lattice vacancies.
  • This getter effect of the vacancy oxygen complexes and oxygen agglomerates present in the second semiconductor region furthermore leads to a diffusion of vacancy points from the first semiconductor region into the second one Semiconductor region, whereby the first semiconductor region depleted at lattice vacancies. Due to the absence of lattice vacancies in the first semiconductor region, no or only very few oxygen precipitates (oxygen precipitates) can form in this semiconductor region, as a result of which a semiconductor region which is poor in oxygen precipitates, a so-called "denuded zone", arises in the first semiconductor region adjoining the first side , Such a semiconductor zone is referred to below as a low-precipitation zone.
  • the described method for producing the precipitate-poor zone also leads to a more homogeneous precipitation-poor zone compared to conventional methods. Due to the very small fluctuations in the implantation dose in the lateral direction, ie transversely to the implantation direction, an implantation process leads to a significantly more homogeneous distribution of the vacancy concentration in the lateral direction than, for example, a conventional Rapid Thermal Annealing (RTA) process in a nitriding atmosphere.
  • RTA Rapid Thermal Annealing
  • An implantation process is also insensitive to thin "parasitic" layers present on the wafer surface, while such layers in a RTA process that acts on the wafer surface significantly affect the rates of surface reactions, and hence vacancy generation.
  • the irradiation of the semiconductor body with high-energy particles to produce crystal defects, in particular to generate vacancies leads to a high concentration of vacancies in the second semiconductor region, thus to a high concentration of oxygen precipitates in the second semiconductor region, since the vacancies cause oxygen precipitation, i. significantly favor the formation of such precipitates.
  • the high vacancy concentration in the second semiconductor region leads to a particularly effective outdiffusion of lattice vacancies from the first semiconductor region into the second semiconductor region.
  • the lattice vacancies can be produced by the irradiation with high-energy particles with a high reproducibility within a wafer and from wafer to wafer, which represents a further advantage over known methods.
  • a further advantage of the present invention is that, by appropriate selection of the irradiation energy and irradiation dose, in contrast to a method which uses nitriding steps for vacancy generation, it is possible to set almost any vacancy distributions in the semiconductor wafer; In particular, very high vacancy concentrations can be generated even in a relatively large depth of the semiconductor crystal.
  • the high-energy particles used for the irradiation are, in particular, non-doping particles, such as protons, noble gas ions, e.g. As helium ions, neon ions or argon ions, or semiconductor ions, for. B. germanium ions or silicon ions.
  • non-doping particles such as protons, noble gas ions, e.g. As helium ions, neon ions or argon ions, or semiconductor ions, for. B. germanium ions or silicon ions.
  • doping particles such as phosphorus ions are also suitable.
  • the penetration depth of the high-energy particles should not be too low for a given irradiation energy, it is preferable to use protons or helium ions which penetrate deeper at a given energy than the heavier particles.
  • FIG 1A schematically shows a side view in cross section of a section of an oxygen-containing semiconductor wafer 100.
  • This wafer is cut from a single crystal produced by a crucible pulling or Czochralski method and is referred to below as CZ wafer.
  • the oxygen concentration of such a CZ wafer is usually above 5 ⁇ 10 17 atoms / cm 3 .
  • the wafer may be undoped or may have a basic doping, in particular a homogeneous base doping, for example an n-base doping, which is already produced when the single crystal is pulled during the Czochralski process.
  • the wafer may have exclusively this basic doping, so that no implantation or diffusion processes-which are always associated with temperature processes-have been subjected to the production of further doped regions and has not undergone an implantation process by which initially only dopant atoms were implanted. without activating them through a temperature process.
  • the wafer 100 has a first side 101, hereinafter referred to as the front side, and a second side 102, which is referred to below as a rear side.
  • Oxygen atoms present in the crystal lattice of the wafer are schematically represented by crosses in FIG. 1A and designated by reference numeral 11.
  • Oxygen atoms, vacancies and vacancy agglomerates are inevitably present in the crystal lattice upon completion of the Czochralski process, in the Figure 1A are shown schematically as circles and designated by the reference numeral 12.
  • a semiconductor region adjoining the front side 101 in the vertical direction of the wafer is referred to below as a first semiconductor region 103 ', while a region adjoining the back surface 102 in the vertical direction of the wafer 100 is referred to below as a second semiconductor region 104'.
  • the aim is to produce in the first semiconductor region 103 ', which adjoins the front side 101, a semiconductor zone which is poor in oxygen precipitates or a denuded zone (denuded zone).
  • FIG. 1B An embodiment of the method according to the invention, reference is made FIG. 1B
  • the wafer 100 is irradiated with high-energy particles via its rear side 102, thereby producing crystal defects, in particular lattice vacancies, in the second semiconductor region 104, such that an increased vacancy concentration exists in the second semiconductor region 104 'compared to the first semiconductor region 103 is.
  • This increased vacancy concentration semiconductor zone is in FIG. 1B
  • the vacancies produced by the irradiation with high-energy particles are understood below to mean, in particular, single vacancies (V), double vacancies (VV) and also vacancy oxygen complexes (OV) Oxygen complexes or other crystal defects occur.
  • Non-doping particles such as protons, noble gas ions or semiconductor ions, are particularly suitable as particles for the irradiation of the wafer 100.
  • a first temperature process takes place in which the wafer is heated to temperatures between 70.0 ° C and 1100 ° C for a certain period of time.
  • the temperature and duration of this temperature process are selected such that vacancy oxygen centers (O 2 V centers) or also higher-order vacancy oxygen complexes form in the second semiconductor region 104 having a high vacancy concentration be that temporally successive at least two different temperatures are set, which are each held for a predetermined period of time.
  • the periods of these individual "temperature plateaus" can be the same length or different lengths.
  • the vacancy oxygen centers generated by the irradiation and the temperature process act as nucleation nuclei for oxygen precipitations, so that stable oxygen agglomerates form in the second semiconductor region 104 during the first temperature process.
  • the nucleation nuclei and oxygen agglomerates also act as gettering centers for impurities present in the semiconductor wafer, or during the subsequent high-temperature processes diffusing into the semiconductor, such as heavy metal atoms, and also act as getter centers for vacancy sites.
  • lattice vacancies from the first semiconductor region 103 diffuse into the second semiconductor region 104 during the first temperature process, as a result of which a vacant semiconductor zone is formed in the first semiconductor region 103.
  • the depletion of the first semiconductor region 103 at vacancies counteracts the formation of oxygen precipitates in the first semiconductor region 103, so that after completion of the temperature process, the first semiconductor region 103 'forms a low-precipitation semiconductor zone which is in Figure 1C designated by the reference numeral 103.
  • the nucleation nuclei and oxygen agglomerates present in the second semiconductor region 104 are stable and become by subsequent temperature processes, such as those used in the production of semiconductor components based on the wafer, no longer resolved.
  • oxygen precipitates may not form in the first semiconductor region 103 during such temperature processes, which would adversely affect the function of a semiconductor device, in particular a power device, since without the presence of voids, precipitate formation becomes very unlikely and / or very likely takes long.
  • the low-precipitate semiconductor zone 103 of the wafer produced by means of the described method is thus also particularly suitable for realizing active component zones, in particular those component zones which serve in power semiconductor components to absorb a blocking voltage of the component.
  • the second semiconductor region 104 having a high precipitate density may be removed after completion of the front-side processes, and then the so-called backside processes required for the completion of the semiconductor device may be performed.
  • the second semiconductor region may also remain.
  • the irradiation of the semiconductor body with high-energy particles and the first temperature process for the generation of the vacancy oxygen centers need not be carried out in direct time sequence.
  • the first temperature process prior to performing the process previously referred to as the "first temperature process", it is possible to perform one or more lower temperature temperature processes to stabilize the post irradiation conditions in the wafer.
  • the temperature processes following the irradiation process can be dedicated temperature processes, which are carried out only for the formation of the vacancy oxygen centers or for stabilization. However, these temperature processes can also be temperature processes which serve a further purpose, for example the production of component structures in the wafer. Such temperature processes are, for example, temperature processes for the activation of dopants after a dopant implantation, temperature processes for the diffusion of dopant atoms into the wafer or temperature processes for the targeted oxidation of component structures.
  • the irradiation process and the temperature processes for the preparation of the vacancy oxygen centers or for stabilization need not take place in close time sequence.
  • the temperature processes can be involved in manufacturing processes of the component manufacturer and can be required for component production anyway required temperature processes.
  • no additional dedicated processes for the formation of the vacancy oxygen centers are required.
  • the only additional process step compared to conventional methods is the irradiation of the wafer with high-energy particles.
  • the duration of the first temperature process in which the wafer is heated to temperatures between 700 ° C and 1100 ° C, can be between one hour and more than 20 hours.
  • the temperature is preferably between 780 ° C and 1020 ° C, preferably one or two temperature plateaus are set at different temperatures.
  • the wafer is initially heated to a temperature between 780 ° C. and 810 ° C. during the first temperature process, for a first time duration shorter than 10 hours, and then for a second time duration that is longer than 10 hours. to heat to a temperature between 980 ° C and 1020 ° C.
  • the first time period is, for example, 5 hours, while the second time period is 20 hours, for example.
  • the wafer 100 is heated to temperatures between 700 ° C and 1100 ° C
  • a "low temperature process” at lower temperatures between 350 ° C and 450 ° C and a duration between 5 hours and 20 hours.
  • This low-temperature step is suitable for the formation of stable nucleation nuclei for oxygen precipitates.
  • the temperature steps for producing the precipitate-poor zone preferably take place in an inert gas atmosphere.
  • the maximum of the vacancy concentration in the semiconductor wafer produced by the particle irradiation can be determined in the method explained on the irradiation conditions, i. H. In particular, on the type of particles used and the irradiation energy with which the particles are irradiated, set comparatively accurate.
  • FIG. 1D shows qualitatively the vacancy distribution in the semiconductor wafer 100 when irradiating the wafer with high-energy particles on the back side 102.
  • the maximum vacancy concentration is in the so-called end-of-range region of the irradiation. This is the range to which the irradiation particles penetrate into the wafer 100 from the backside 102.
  • the distance to the back side 102 of the wafer denotes
  • al denotes the distance of the maximum vacancy concentration starting from the back side 102.
  • This position al the maximum
  • the concentration of vacancies depends on the radiation therapy and, in the case of a proton implantation with an implantation energy of 2.25 MeV, lies in the range between 55 and 60 ⁇ m starting from the rear side 102.
  • the irradiation with protons can be perpendicular or at an angle of inclination to the rear side 102, for example at an angle between 5 ° and 10 °.
  • the maximum vacancy concentration in the end-of-range region is about 7 ⁇ 10 18 vacancies / cm 3 .
  • the vacancy concentration at the above-mentioned implantation dose in the range of about 5 x 10 17 voids / cm 3.
  • the dimensions of the low-precipitation semiconductor zone 103 in the vertical direction of the wafer are also dependent on the irradiation conditions, in particular the irradiation energy.
  • the precipitate-lean semiconductor zone 103 is formed in the described method in the region in which no additional vacancies are generated by the particle irradiation.
  • the vacancy reduction in the first semiconductor region can take place more effectively during the first temperature process, the smaller the dimensions of the first semiconductor region 103 in the vertical direction or the higher the vacancy concentration in the second semiconductor region and the greater the vertical extent of the second semiconductor region 104.
  • the particle irradiation is preferably carried out in such a way that the end-of-range region of the irradiation is as close as possible to the low-precipitation semiconductor zone 103 which adjoins the front side 101.
  • Typical irradiation energies are in the range of 2 ... 5 ... 10 MeV at thicknesses of the wafer between 400 ... 700 ... 1000 ⁇ m.
  • lower irradiation energies for example in the range of 70-200kev, are also conceivable in order to produce precipitate-rich zones in the semiconductor crystal.
  • Such irradiation energies can be achieved by commercially available implantation equipment.
  • the wafer Before carrying out the particle irradiation, the wafer can optionally be subjected to a second temperature process in which the wafer is heated to temperatures greater than 1000 ° C. in a moist and / or oxidizing atmosphere.
  • a second temperature process in which the wafer is heated to temperatures greater than 1000 ° C. in a moist and / or oxidizing atmosphere.
  • Such a procedure is from the above-mentioned EP 0769809 A1 is known and serves specifically to inject interstitial silicon atoms into the wafer, wherein the depth to which these silicon atoms are injected depends on the duration of the temperature process and is the greater, the longer this temperature process is performed.
  • the injection of these interstitial silicon atoms already leads to a reduction of vacancies, in particular in the near-surface regions of the semiconductor wafer, in particular to a reduction of vacancy agglomerates and eliminates so-called D defects in the semiconductor wafer.
  • the pre-annealing of the semiconductor wafer by means of the second temperature process can in particular serve to produce the same "initial states" of several wafers processed by the described method, thereby producing wafers having the same properties under the same process conditions.
  • This procedure is based on the knowledge that individual wafers cut off from different single crystals can differ with regard to their vacancy concentrations and with regard to the so-called D defect distributions. In particular, by this procedure, previous precipitates can be resolved, and the vacancy concentration in the thus treated semiconductor crystal can be lowered, which greatly reduces the probability of precipitate formation in subsequent high-temperature steps.
  • the penetration depth of the interstitial silicon atoms can also be limited to the vertical extent of the semiconductor zone 103. Of course, however, it is also possible to expose both sides 101, 102 of the wafer to a moist and / or oxidizing atmosphere during this preheating.
  • the wafer after or before carrying out the first temperature process by which the nucleation centers and oxygen agglomerates are generated, to subject the wafer to a further temperature process in which at least the first semiconductor zone 103 is heated in such a way that oxygen atoms from this first semiconductor zone cross the Diffuse front 101 of the wafer.
  • the temperatures of this further temperature process are, for example, in the range between 900 ° C and 1250 ° C.
  • the oxygen concentration in the precipitate-poor semiconductor zone 103 is further reduced, which further reduces the probability of the formation of oxygen precipitates in this semiconductor zone during subsequent temperature processes.
  • the reduction of oxygen in the low-precipitation semiconductor zone reduces the risk of formation of a thermal donor.
  • Such thermal donors may be formed in a crystal lattice in the presence of interstitial oxygen and in temperature processes at temperatures between 400 ° C and 500 ° C.
  • All of the above-explained temperature processes can be realized as conventional furnace processes in which the wafer is heated to the desired temperature in an oven.
  • trenches 110 into the semiconductor body from the rear side 102 before performing the particle irradiation.
  • the high-energy particles penetrate both the backside 102 and the trenches 110 into the second semiconductor region 104 of the wafer.
  • the trenches offer a further possibility of influencing the penetration depth of the high-energy particles into the semiconductor wafer 100.
  • these vacancies also have the possibility of subjecting the semiconductor wafer to a thermal process in which the backside 102 of the wafer is exposed to a nitriding atmosphere while the front surface is exposed, for example, by deposition an oxide is protected from such nitriding atmosphere.
  • the temperature process in the nitriding atmosphere causes generation of vacancies in the second semiconductor region 104, but the achievable vacancy concentration is lower than in the previously discussed particle irradiation.
  • the wafer is preferably heated rapidly, for example by means of an RTA step, and then cooled comparatively slowly, which in the above-mentioned US 6,849,119 B2 is explained.
  • the production of lattice vacancies by a temperature process in a nitriding atmosphere is particularly suitable in combination with the basis of FIG. 2 explained production of trenches 110 starting from the back side 102 of the semiconductor wafer.
  • the method explained above for producing a low-precipitation semiconductor zone is also suitable for producing a precipitation-poor semiconductor zone in the semiconductor substrate of an SOI substrate.
  • an SOI substrate has a semiconductor substrate, an insulating layer arranged on the semiconductor substrate, and a semiconductor layer arranged on the insulating layer.
  • Such a substrate may, for. Example, be prepared by a layer assembly with the insulating layer and the semiconductor layer is bonded to the semiconductor substrate by means of a wafer bonding process.
  • the semiconductor substrate may in particular be a CZ wafer.
  • FIG. 1A For example, an insulation layer 302 and a semiconductor layer 301 that complement the CZ wafer to form an SOI substrate are shown in phantom.
  • a precipitation-poor semiconductor zone can be produced in the wafer 100 in a region subsequent to the insulation layer 302.
  • This procedure is particularly advantageous if an electric field is built up in the region of the SOI substrate adjoining the insulating layer during operation of the component. So far, this area had to be performed as an epitaxially deposited semiconductor layer to z. B. to keep the generation caused by reverse current within tolerable and narrow tolerance limits. Thanks to the described method, the generation of this complex and expensive epitaxial layer can be dispensed with, or such an epitaxial layer can be made at least considerably thinner and thus more cost-effective than hitherto customary.
  • the semiconductor layer 301 present above the insulating layer 302 can also be used as a low-precipitation zone of a CZ base material using the method explained.
  • a further CZ semiconductor wafer which comprises the later zone 301, subjected to the method explained, so that a low-precipitate, adjacent to a surface of the disc zone is formed.
  • This further slice is then bonded to the semiconductor substrate, the low-precipitation zone of the further slice facing the substrate 100 or the insulating layer 302.
  • a precipitate-rich zone (not shown) of this further disc is removed again after the wafer bonding, for example by grinding and / or etching.
  • Waferbondmaschinen itself are basically known, so that no further comments are required.
  • two semiconductor surfaces to be bonded are brought together, one or both of which may be oxidized, followed by a temperature process to join the two surfaces.
  • the described method can also be combined very well with the so-called SIMOX technologies for producing an SOI substrate. Ie. First, the precipitation-poor zone 103 is generated by means of the described method, and then the insulation layer is produced in this zone 103 by means of an oxygen implantation.
  • the semiconductor wafer which has a precipitate-free or at least precipitate-free semiconductor zone 103 in the area of its front side 101 after the described treatment, is particularly suitable for realizing vertical power components, as will be explained below.
  • the wafer may have a basic doping, for example a n-type fundamental doping, which is already produced when the single crystal is pulled during the Czochralski process.
  • the low-precipitation semiconductor zone 103 can be used in particular for realization serve a blocking voltage of the power device receiving semiconductor zone.
  • This method may be used in addition to making n-type fundamental doping during the pulling of the single crystal, but may also be applied to fabricating an n-type semiconductor region on an undoped CZ wafer that acts like a ground doped zone, ie, in the vertical direction at least a large part of their vertical extent has an approximately constant doping.
  • the latter is particularly advantageous because the production of a basic doping of the wafer during the pulling of the single crystal due to the oxygen precipitates present leads to unsatisfactory results, in particular to an inhomogeneous and poorly reproducible doping.
  • protons are implanted via the front side 101 into the low-precipitation semiconductor zone 103 of the wafer 100.
  • the implantation direction may be perpendicular to the front side 101, but may also extend at an angle with respect to this front side 101.
  • the proton implantation causes crystal defects in the region of the precipitate-poor semiconductor zone 103 which is irradiated by protons.
  • protons are introduced into the low-precipitation semiconductor zone 103 by the proton implantation.
  • the dimensions of a crystal defects having, penetrated by protons zone in the vertical direction, starting from the front side 101 are dependent on the implantation energy. The dimensions of this zone are greater, the higher the implantation energy, the deeper the protons penetrate into the wafer 100 via the front side 101.
  • the proton irradiation is followed by a temperature process in which the wafer 100 is heated to temperatures between 400 ° C. and 570 ° C., at least in the area irradiated with protons, resulting in hydrogen-induced donors from the crystal defects produced by the proton irradiation and the protons introduced ,
  • the temperature during this temperature process is preferably in the range between 450 ° C and 550 ° C.
  • the protons are mainly introduced into the end-of-range region of the irradiation.
  • the position of this region starting from the front side 101 is dependent on the implantation energy.
  • the end-of-range region forms the "end" of the area irradiated by the proton implantation in the vertical direction of the wafer 100.
  • the formation of hydrogen-induced donors presupposes - as already explained - the presence of suitable crystal defects and the presence of protons.
  • the duration of the temperature process is preferably selected so that the protons introduced mainly into the end-of-range region diffuse to a significant extent in the direction of the front side 101, thereby to obtain the most homogeneous possible n-doping in the irradiated region of the precipitate-rich semiconductor zone 103 produce.
  • the duration of this temperature process is between one hour and 10 hours, preferably between 3 and 6 hours.
  • n-doped semiconductor region 105 in the low-precipitate semiconductor zone 103 of the wafer 100.
  • the n-type semiconductor region 105 extends from the front side 101 to a depth d0 into the wafer 100, this depth depending on the implantation energy as explained.
  • FIG. 3C shows an example of a doping profile of this n-type semiconductor zone 105.
  • N D0 denotes the basic doping of the wafer 100 before the doping process is carried out.
  • 105 the n-type semiconductor region, starting from the front side 101 of an approximately homogeneous doping profile with a doping concentration N D, which increases in an end portion of the n-type semiconductor region 105 to a maximum doping concentration N Dmax and thereafter decreases to the basic doping N D0 ,
  • the end region of the n-type semiconductor zone, in which the doping initially increases and then decreases to the basic doping, results from the end-of-range region of the proton implantation, in which the majority of the protons are incorporated during the implantation.
  • the temperature process is selected such that the n-type semiconductor zone 105 produced by the proton implantation and the subsequent temperature treatment has an area with at least approximately homogeneous doping, which in the vertical direction of the semiconductor body 100 is at least 60%, better greater than 80%, the extension of the n-type semiconductor region 105 extends, assuming as a vertical extent a distance between the implanted surface and the so-called end-of-range implantation.
  • the end-of-range refers to the position at which the proton concentration is greatest immediately after implantation.
  • at least approximately homogeneous doping is meant in this context that the ratio between maximum doping concentration and minimum doping concentration in the region of homogeneous doping is at most 3.
  • this ratio is at most 2, in further embodiments it is provided that this ratio is a maximum of 1.5 or 1.2.
  • the above-explained method for producing the n-type doped semiconductor region 105 in a low-precipitation semiconductor zone of a CZ wafer can be carried out by any method for producing such a low-precipitation semiconductor region.
  • the oxidation can also be carried out in particular in an atmosphere of an oxygen-containing gaseous dopant compound, such as POCl 3 .
  • an oxygen-containing gaseous dopant compound such as POCl 3 .
  • POCl 3 oxygen-containing gaseous dopant compound
  • Such an oxidation method can also be combined with the previously described method comprising an irradiation process and at least one temperature process by carrying out the irradiation and temperature process after the oxidation process has been carried out.
  • the removal of the oxide layer can be carried out, for example, by means of an etching process.
  • the oxidation of the wafer surface and the etching of the oxide layer lead to a roughening of the wafer surface to an extent which is at least unsuitable for the further production of integrated circuits (ICs).
  • the surface of the wafer is therefore preferably polished before further method steps, for example the method steps for producing the n-doped zone 105 and / or method steps for the realization of components, are carried out.
  • the semiconductor zone 105 having an n-doping with hydrogen-induced donors and produced by the method explained above is particularly suitable for realizing a reverse-bias voltage-receiving semiconductor zone of a power semiconductor device.
  • a zone is for example the drift zone of a MOSFET, the drift zone or n-base of an IGBT or the drift zone or n-base of a diode.
  • the n-type semiconductor zone 105 can also be produced such that the maximum of the doping concentration lies in the region 104 comprising oxygen agglomerates, so that the low-precipitation zone 103 receives a homogeneous n-type doping as a result of the doping process.
  • a single crystalline epitaxial layer 200 may be formed on the front side 101 above the low precipitate semiconductor zone 103.
  • the doping concentration of this epitaxial layer 200 is preferably matched to the doping concentration of the low-precipitate semiconductor zone 103 or the n-doped semiconductor zone 105 present in the precipitate-poor semiconductor zone 103 and moreover to the requirements of the component.
  • the adjustment of the doping concentration of the epitaxial layer 200 takes place in a known manner during the deposition process of this epitaxial layer or optionally also by proton irradiation in combination with a suitable heat treatment according to the method explained above.
  • the semiconductor wafer 100 which has been processed by means of the previously explained treatment methods, is suitable for the production of vertical power semiconductor components, which is described below with reference to FIGS FIGS. 5 and 6 is explained.
  • the starting material for the power semiconductor components forms the wafer 100, optionally on the basis of FIG. 4 explained epitaxial layer 200 may be applied.
  • epitaxial layer 200 For the following explanation, the presence of such an epitaxial layer 200 is assumed.
  • this epitaxial layer 200 can also be dispensed with, in particular if the precipitation-poor semiconductor zone 103 in the vertical direction of the wafer 100 has a sufficiently large dimension for the realization of active device zones, in particular for the realization of a blocking voltage receiving component zones of the power semiconductor component ,
  • FIG. 5 shows in side view in cross section a vertical power MOSFET, which was prepared on the basis of a treated according to the previously discussed method CZ wafer 100.
  • the MOSFET has a semiconductor body which is penetrated by a portion 100 'of the treated wafer (100 in FIGS FIGS. 1 to 4 ) and in the example is formed by an epitaxial layer 200 applied to the wafer.
  • Reference numeral 201 in the example denotes a front side of the epitaxial layer, which simultaneously forms the front side of the semiconductor body.
  • the wafer portion 100 ' is in a manner not shown by removing the wafer 100 from the rear side thereof (reference numeral 102 in the FIGS. 1 to 4 ) emerged.
  • the reference numeral 111 denotes the surface of this wafer section 100 'which is present after the removal and simultaneously forms the rear side of the semiconductor body.
  • the MOSFET is designed as a vertical trench MOSFET and has a source zone 21, a body zone 22 adjoining the source zone 21 in the vertical direction, a drift zone adjoining the body zone 22 in the vertical direction 23 and a subsequent to the drift zone 23 in the vertical direction drain zone 24.
  • the source zone 21 and the body zone 22 are in the in FIG. 5 shown component disposed in the epitaxial layer 200.
  • a gate electrode 27 is provided, of which in FIG. 5 two electrode sections are shown and which is arranged in a trench, which extends from the front side 201 in the vertical direction into the semiconductor body.
  • the gate electrode 27 is dielectrically insulated from the semiconductor body by means of a gate dielectric 28, usually an oxide layer.
  • the production of the source and body zones 21, 22 can take place in a known manner by means of implantation and diffusion steps.
  • the gate electrode is produced by etching the trench, depositing a gate dielectric layer in the trench, and depositing an electrode layer in the trench.
  • the source zone 21 is contacted by a source electrode 25, which extends in sections in the vertical direction of the semiconductor body into the body zone 22, thereby short-circuiting the source zone 21 and the body zone 22 in a known manner.
  • the drain region 24 is contacted by a drain electrode 26 applied to the back surface 111.
  • the drift zone 23 of the MOSFET is formed in sections through the epitaxial layer 20 and in sections through the low-precipitation semiconductor zone 103 of the wafer section 100 '.
  • the drain zone 24 is a semiconductor zone which is heavily doped in comparison to the drift zone 23 and which can be produced, for example, by implantation of dopant atoms via the rear side 111.
  • the drain zone 24 can be arranged completely in the low-precipitation semiconductor zone 103, but can also be used in a semiconductor zone containing oxygen agglomerates after the etching back or grinding back (reference symbol 104 in FIGS FIGS. 1 to 3 ) can be arranged.
  • the component is formed by the drift zone, which serves to receive an applied blocking voltage in the case of a blocking component, only by sections of the precipitation-poor semiconductor zone 103. Otherwise, oxygen agglomerates present in the drift zone 23 would degrade the performance of the component, in particular its dielectric strength and leakage current behavior.
  • the dielectric strength of the illustrated power MOSFET is significantly dependent on the dimensions of the drift zone 23 in the vertical direction and beyond the doping concentration of this drift zone.
  • the wafer portion 100 'remaining after the wafer has been ground back during the device fabrication process may comprise only the previously generated low-precipitation semiconductor zone 103, but may also include portions of the oxygen agglomerates 104 in the region of the back surface 102, such zone containing only oxygen agglomerates Realization of the highly doped drain zone 24 and not for the realization of a reverse voltage receiving drift zone 23 may serve.
  • an epitaxial layer 200 can be dispensed with, in particular, if the dimensions of the precipitation-poor semiconductor zone 103 in the vertical direction are sufficiently large to realize a drift zone with a thickness sufficient for a desired dielectric strength.
  • the illustrated vertical power MOSFET is in particular an n-power MOSFET.
  • the source zone 21, the drift zone 23 and the drain zone 24 are n-doped, while the body zone 22 is p-doped.
  • the doping of the drift zone 23 can be generated according to the method explained above by means of a proton implantation in the front of the pane and a subsequent annealing step. These steps for doping the drift zone 23 preferably take place only after the production of the source and body zones 21, 22 and the gate oxide 28, since these fabrication steps require temperatures that are far above 600 ° C., so that a proton-induced doping would disappear. Fabrication steps requiring temperatures below about 430 ° C - e.g. the tempering of the metallization or of deposited polyimide layers, on the other hand, can be done later, i. after the doping of the drift zone 23, take place. In this case, the temperature budget of the subsequent production steps can be credited to the temperature budget for annealing the proton-induced doping of the drift zone 23. Such further heat treatment can then be carried out correspondingly shorter or even completely eliminated.
  • bipolar power devices such as a trench IGBT.
  • the structure of such a trench IGBT corresponds to the structure of in FIG. 5 shown vertical power MOSFET, with the difference that instead of a the same type of conductivity as the drift zone 23 having drain zone 24 a complementary to the drift zone 23 doped emitter region 24 is present.
  • the emitter zone 24 in the drift zone 23 may be preceded by a field stop zone 29 which is doped with the same conductivity type as the drift zone 23, but higher than the drift zone 23.
  • This field stop zone 29 may be connected to the emitter zone 24, but may also be arranged at a distance from the emitter zone 24. However, the field stop zone 29 is closer to the emitter zone 24 than to the body zone 22.
  • the production of such a field stop zone 29 in the CZ wafer 100 can be carried out by means of a proton implantation and a subsequent temperature step.
  • the proton implantation can take place in particular via the rear side 102 of the wafer 100.
  • the distance of the field stop zone 29 to the back is dependent on the implantation energy used.
  • the method for producing the field stop zone differs from the method for producing the semiconductor zone having the n base doping 105 by the duration and / or temperature of the temperature step.
  • a diffusion of the protons should be achieved to a significant extent in the direction of the implantation side in order to obtain the most homogeneous possible doping over a region as wide as possible in the vertical direction.
  • the field stop zone 29 should, in contrast, be limited as exactly as possible in the vertical direction.
  • the temperature and / or the duration of the temperature step for producing the field stop zone 29 is less than the temperature and / or duration when the n zone 105 is produced.
  • the temperature of the temperature process during the production of the field stop zone 29 is, for example, in the range between 350 ° C and 400 ° C, the duration of the temperature process is between 30 minutes and 2 hours.
  • the field stop zone can take place completely or at least partially during the method steps for producing the n-basic doping.
  • protons are implanted into the wafer via the front side 101 to produce the n-type basic doping. These protons then diffuse out of the end-of-range region under the influence the temperature process towards the front. This diffusion process can be adjusted over the duration and the temperature of the temperature process so that in the end-of-range region, a higher doping is produced than the n-basic doping in the intermediate region located between the end-of-range region and the front side.
  • the temperature and / or the duration of the temperature process for producing a n-type basic doping with simultaneous production of a field stop zone are lower than in the process for the exclusive production of the n-type basic doping.
  • the implantation energy of the proton radiation should be adjusted so that the penetration depth of the protons is less than the wafer thickness of the wafer.
  • An additional doping of the field stop zone can be achieved by the method explained above, in which a proton implantation is carried out via the back side.
  • the drift zone 23 is usually n-doped in an IGBT. Accordingly, the body and emitter regions 22, 24 are p-doped.
  • the production of an n-doped field stop zone 29 can, for example, by proton implantation on the back 111 and over the back 102 of the wafer not yet removed and a subsequent temperature process at temperatures between 350 ° C and 420 ° C and more preferably in the temperature range between 360 ° C and 400 ° C take place.
  • the basic doping of the drift zone 23 is also preferably generated in the manner explained by a proton implantation in combination with a suitable annealing step, wherein the proton implantation preferably takes place via the front side 201. Alternatively or additionally, however, this proton implantation can also take place via the wafer rear side 111, particularly preferably after a backside thinning process has been carried out.
  • FIG. 6 shows in side view in cross section a realized on the basis of the treated wafer base material vertical power diode.
  • the reference numeral 201 is in FIG. 6 the front side of a semiconductor body in which the diode is integrated, while reference numeral 111 denotes a back side of this semiconductor body.
  • the semiconductor body comprises a wafer section 100 ', which can be ground by grinding back on the basis of FIG FIGS. 1 to 3 Wafer 100 is obtained. On this wafer portion 100 'is optionally the basis of FIG. 4 explained epitaxial layer 200 applied.
  • the power diode has a p-type emitter zone or anode zone 31, a base zone 32 adjoining the p-emitter zone and an n-emitter zone or cathode zone 33 adjoining the base zone 32 in a vertical direction.
  • the base zone 32 is either p-doped or n-doped and serves in reverse-biased power diode for receiving the applied reverse voltage.
  • the base region 32 is formed in the example by a portion of the epitaxial layer 200 and by a portion of the low-precipitation semiconductor zone 103 of the wafer portion 100 '.
  • the n-type emitter 33 may also be completely formed in the low-precipitate semiconductor region 103.
  • This n-emitter is generated, for example, by implantation of n-dopant atoms over the backside 111.
  • the n-emitter 33 can also be partially covered by the semiconductor zone comprising oxygen agglomerates (reference numeral 104 in FIGS FIGS. 1 to 3 ) of the wafer.
  • the decisive factor is that the reverse voltage receiving base zone 32 is formed only by low-precipitation semiconductor zones 103 of the wafer.
  • the anode zone 31 of the diode is contacted by an anode electrode 34, which forms an anode terminal A.
  • the cathode zone 33 is contacted by a cathode electrode 35, which forms a cathode terminal K.

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Claims (15)

  1. Procédé de traitement d'une plaquette (100) semi-conductrice contenant de l'oxygène non dopé ou ayant exclusivement un dopage de base, qui a une première face (101), une deuxième face (102) opposée à la première face (101), une première zone (103') semi-conductrice se raccordant à la première face (101) et une deuxième zone (104') semi-conductrice se raccordant à la deuxième face (102), ayant les stades de procédé suivant :
    on expose la deuxième face de la plaquette (100) à des protons ou à des ions hélium de manière à créer des lacunes réticulaires dans la deuxième zone (104') semi-conductrice.
  2. Procédé suivant la revendication 1, dans lequel, en outre :
    on effectue un premier processus de mise en température, dans lequel on porte la plaquette (100) à des températures comprises entre 700°C et 1 100°C.
  3. Procédé suivant la revendication 2, dans lequel on choisit la durée du processus de mise en température de façon à ce que des agglomérats d'oxygène se forment dans la deuxième zone (104') semi-conductrice et que des lacunes réticulaires diffusent de la première zone (103') semi-conductrice dans la deuxième zone (104') semi-conductrice.
  4. Procédé suivant la revendication 2 ou 3, dans lequel la durée du premier processus de mise en température est comprise entre 1 heure et 20 heures.
  5. Procédé suivant l'une des revendications 2 or 3, dans lequel on porte la plaquette pendant le processus de mise en température d'abord, pendant une première durée qui est plus courte que 10 heures, à une température comprise entre 790° C et 810° C et ensuite, pendant une deuxième durée qui est plus longue que 10 heures, à une température comprise entre 985° C et 1 015° C.
  6. Procédé suivant l'une des revendications précédentes, dans lequel une épaisseur de la plaquette est comprise entre 400 µm et 1 000 µm et dans lequel l'énergie d'exposition est comprise entre 70 keV et 10 meV.
  7. Procédé suivant l'une des revendications 1 à 6, dans lequel la dose d'implantation de protons est comprise entre 1·1013 cm-2 et 1 ·1015 cm-2.
  8. Procédé suivant l'une des revendications 2 à 7, qui comprend le stade suivant de procédé avant l'exposition de la deuxième face (102) de la plaquette (100) :
    - on effectue un deuxième processus de mise en température, dans lequel on porte la plaquette (100) à une température supérieure à 1 000° C et dans lequel on soumet au moins la première face (101) à une atmosphère humide et/ou oxydante.
  9. Procédé suivant la revendication 8, dans lequel on soumet la première et la deuxième faces à une atmosphère humide et/ou oxydante pendant le processus de mise en température.
  10. Procédé suivant l'une des revendications 2 à 9, qui a,
    - on effectue un troisième processus de mise en température, dans lequel on chauffe la première zone (103) semi-conductrice de manière à ce que des atomes d'oxygène diffusent de cette première zone (103) semi-conductrice par la première face (101) de la plaquette.
  11. Procédésuivant l'une des revendications précédentes, qui comprend la production d'une zone (29) d'arrêt de champ à dopage n dans la plaquette en effectuant des stades de procédé suivants :
    - on expose la plaquette (100) par au moins l'une des premières et des deuxièmes faces (101, 102) à des protons en créant ainsi des défauts cristallins dans la première zonz semi-conductrice,
    - on effectue un processus de mise en température, dans lequel on porte la plaquette (100) de température comprise entre 350°C et 550° C, de manière à créer une zone (29) d'arrêt de champ ayant des donneurs induits par de l'hydrogène.
  12. Procédé suivant l'une des revendications 3 à 11, dans lequel l'exposition de la deuxième face (102) de la plaquette comprend au moins deux stades d'exposition à des énergies d'exposition différentes.
  13. Procédé suivant la revendication 12, dans lequel le processus de mise en température comprend au moins deux stades de mise à température à distance dans le temps, dans lesquels la plaquette (100) est chauffée respectivement, au moins l'un de ces stades de mise en température se trouvant dans le temps entre deux stades d'exposition.
  14. Procédé de production d'un substrat SOI, qui comprend les stades de procédé suivants :
    - on se procure une première et une deuxième plaquettes semi-conductrices, qui ont respectivement une première et une deuxième faces,
    - on effectue le procédé suivant l'une des revendications 3 à 13, pour au moins l'une des deux plaquettes semi-conductrices pour produire dans celle-ci sur sa première face, ensuite dans l'une au moins des deux plaquettes, une zone pauvre en précipité,
    - on relie la première et la deuxième plaquettes semi-conductrices de façon à ce que leurs premières faces soient tournées l'une vers l'autre et de façon à ce qu'il y ait un couche isolante entre les premières faces des plaquettes semi-conductrices.
  15. Procédé suivant l'une des revendications 3 à 13, qui comprend, pour la production d'une zone à dopage n dans la plaquette semi-conductrice les stades de procédés suivants :
    - on implante des protons par la première face (101) dans la plaquette en créant ainsi des défauts cristallins dans la première zone (103) semi-conductrice et en implantant ainsi des protons au sein de la plaquette semi-conductrice jusque dans une zone End-Of-Range en fonction d'une énergie d'implantation,
    - on effectue un autre processus de mise en température, dans lequel on porte la plaquette (100) au moins dans la zone de la première face (101) à des températures comprises entre 400° C et 570° C, de manière à créer une zone semi-conductrice à dopage n ayant des donneurs induits par de l'hydrogène et dans lequel on choisit la durée et la température de façon à ce que des protons diffusent de la zone End-Of-Range en direction de la première face (101), de sorte que la zone (105) semi-conductrice à dopage n a une région à dopage homogène au moins approximativement, qui s'étend dans la direction verticale du corps (100) semi-conducteur au moins sur 60% ou au moins sur 80% d'une distance entre la zone End-Of-Range et la première face (101) et qui a un dopage homogène au moins approximativement produit par l'implantation de protons, de manière à ce qu'un rapport entre une concentration maximale de dopage et une construction minimale de dopage et une construction minimale de dopage dans la région de dopage homogène soit au maximum de 3.
EP07702904A 2006-01-20 2007-01-19 Procede de traitement d'une plaquette semi-conductrice contenant de l'oxygene et composant semi-conducteur Not-in-force EP1979934B1 (fr)

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DE102006041402 2006-09-04
PCT/EP2007/000475 WO2007085387A1 (fr) 2006-01-20 2007-01-19 Procédé de traitement d'une plaquette semi-conductrice contenant de l'oxygène et composant semi-conducteur

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EP1979934A1 (fr) 2008-10-15
DE502007003501D1 (de) 2010-06-02
CN103943672A (zh) 2014-07-23
ATE465510T1 (de) 2010-05-15
JP5358189B2 (ja) 2013-12-04
EP2058846B1 (fr) 2011-08-31
WO2007085387A1 (fr) 2007-08-02
ATE522927T1 (de) 2011-09-15
JP2015122521A (ja) 2015-07-02
EP2058846A1 (fr) 2009-05-13
JP2013153183A (ja) 2013-08-08
JP2017224837A (ja) 2017-12-21
JP2009524227A (ja) 2009-06-25
CN103943672B (zh) 2020-06-16

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