EP2179443A1 - Module et fabrication d'un tel module - Google Patents

Module et fabrication d'un tel module

Info

Publication number
EP2179443A1
EP2179443A1 EP08774783A EP08774783A EP2179443A1 EP 2179443 A1 EP2179443 A1 EP 2179443A1 EP 08774783 A EP08774783 A EP 08774783A EP 08774783 A EP08774783 A EP 08774783A EP 2179443 A1 EP2179443 A1 EP 2179443A1
Authority
EP
European Patent Office
Prior art keywords
component
sintering
substrate
recess
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08774783A
Other languages
German (de)
English (en)
Inventor
Daniel Wolde-Giorgis
Thomas Kalich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2179443A1 publication Critical patent/EP2179443A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering or brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B23K35/025—Pastes, creams or slurries
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/251—Organics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07336—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/342—Dispositions of die-attach connectors, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612—Composite web or sheet

Definitions

  • the invention relates to an assembly comprising a substrate and at least one component attached thereto by sintering with a sintering agent, in particular sintering paste.
  • the invention relates to a method for producing an assembly with a substrate and at least one by sintering with a sintering agent, in particular sintered paste, attached thereto component.
  • the sintering agent is first applied to the planar substrate. Subsequently, the component is applied to the sintering agent or pressed into the sintering agent, which due to lack of adhesive properties sufficient prefixing of the component is not guaranteed.
  • the sintering process itself requires pressurization in order to ensure sufficient contact of the colloids contained in the sintering agent with each other and with the substrate and the component.
  • the pressure is realized via a soft, provided with component-specific impressions silicone stamp. The stamp is used to align and fix the assembly consisting of the substrate, the sintering agent and the component for the sintering process.
  • the embossing of the stamp allows an isostatic / quasi-isostatic pressurization of the component. Due to the poor adhesive properties of the sintering paste, however, it may happen that the component already slips out of its intended position before or during initiation of the pressure force and / or that part of the sintering agent is squeezed out of the position to be joined and adheres to the stamp, which is too one increased rejection and carryover of sintering agent leads to the stamp.
  • the sintering agent is arranged in a recess of the substrate which accommodates the component at least in regions. It is therefore provided that the substrate has a recess which receives the component at least in regions, wherein in the recess, the sintering agent for the sintering or fastening operation is arranged in the recess. Since the component is now located in the recess of the substrate, it is possible to position the component on the substrate so that it does not leave its intended position before or during the sintering process. Furthermore, it is prevented by the formation of the recess in the substrate that the sintering agent introduced therein when introducing the
  • Compressive force is squeezed out of the site to be joined and / or adhering to the pressure force applying stamp.
  • the depression particularly preferably has an outline which essentially corresponds to the contour of the component.
  • the depression has areas (catchment spaces) into which excess sintering agent can escape when the pressure force is introduced.
  • the stamp surface preferably yielding elastically, so that a uniform (isostatic) pressure distribution is ensured. The positioning and alignment of the component is ensured by the recess.
  • the sintering agent is a silver sintered paste, which expediently consists of chemically stabilized silver colloids.
  • the sintering agent is a sintered solid.
  • the stabilizing constituents of the paste are burned out so that the silver colloids come into direct contact with each other and with the material of the component and the substrate.
  • the component is an electrical / electronic component, in particular a line semiconductor, such as a MOSFET.
  • the substrate is a stamped grid or a
  • the sintering agent is introduced into a recess of the substrate receiving the component at least in regions. It is thus provided that the sintering agent is first introduced into the recess and then the component, wherein the component is placed or pressed onto the sintering agent. Of course, it would also be conceivable that the component carries the sintering agent with it.
  • a stamp having a flat stamp surface is advantageously used, wherein the stamp surface is elastically deformable, so that when applying the sintering pressure, the component can be pressed into the stamp at least partially. This ensures on the one hand that a uniform pressure distribution is applied to the component and a displacement of the component is prevented.
  • a silicone stamp is used for this purpose.
  • the recess is made such that its outline corresponds substantially to the contour of the component, so that the component can not be moved out of the recess and can be clearly aligned or positioned by the outline of the depression on or on the substrate.
  • the sintering agent used is a silver sintering paste which expediently comprises silver colloids.
  • a stamped grid or a printed circuit board is used as the substrate.
  • the component is arranged in a depression of the stamped grid or the printed circuit board in which the sintering agent or the preferred silver sintering paste has previously been introduced.
  • the stamp which is advantageously designed as a silicone stamp
  • the silver sintering paste or the sintering agent can not leak undefined on the substrate, so that, for example, no sintering agent hangs on the stamp.
  • FIG. 2 shows an embodiment of an advantageous method for
  • Figure 3 shows a substrate of the assembly
  • FIG. 4 shows the substrate of the module fitted with a component.
  • FIG. 1 shows, in a schematically illustrated embodiment, an advantageous assembly 1.
  • DBC Direct Bonded Copper
  • the advantageous assembly 1 allows the safe creation of a silver-sintered connection, which allows easy positioning of the component 3 on the substrate 5 and also prevents carryover of sintering agent.
  • the substrate 5 has on a surface 6 a recess 7 into which the component 3 or the power semiconductor 2 can be introduced.
  • a sintering agent 8 which is formed as a silver sintered paste 9, arranged so that the component 3 is applied during assembly on the silver sintered paste 9 in the recess 7.
  • FIG. 3 shows the substrate 5 in a plan view of the surface 6.
  • the recess 7 formed in the substrate 5 in this case has a substantially quadratic contour 10, which advantageously corresponds substantially to the contour of the component 3 / power semiconductor 2, so that the component 3 is positioned and aligned by placing it in the recess 7 on the substrate 5, as shown in FIG.
  • FIG. 4 shows the substrate 5 from FIG. 3 with the power semiconductor 2 or component 3 introduced into the recess 7.
  • the alignment of the component 3 on the substrate 5 can be recognized by means of the recess 7.
  • the component 3 is acted upon by a punch 11 with a compressive force in the direction of the arrow 12.
  • the punch 11 has a flat in the unloaded state stamp surface 13 which is elastically deformable, so that upon application of the component 3, as shown in Figure 2, partially pressed into the punch 11. Due to the elastic design of the flat stamp surface 13 is a quasi-isostatic
  • the punch 11 presses the assembly 1 for generating the necessary pressure force for the sintering operation against a counter plate 14th
  • the recess 7 is advantageously formed so deep that it can accommodate a desired amount of sintering agent 8 / silver sintering paste 9 and the component 3 at least partially.
  • any common substrate type come into question, wherein an upper-side metallization 15 must be sufficiently thick in order to realize sufficient current carrying capacity at the desired amount of silver sintered paste 9 can.
  • the printed circuit board 4 shown in section in FIGS. 1 and 2 has, in addition to the metallization 15, a further metallization 16 which is arranged on the opposite side of a substrate carrier 17 carrying the metallizations 15 and 16.
  • the metallizations 15, 16 are in this case formed as conductor tracks.
  • the component 3 Due to the advantageous recess 7, the component 3 also retains its position during the sintering process when the component 3 is subjected to the sintering pressure force. In addition, it is prevented that the silver sintered paste 9 exits uncontrollably on the substrate 5. Through the recess 7, the silver sintered paste 9 is held in position.
  • the depression 7 causes the component 3 to be movable only in the frame defined by the outline 10 of the depression 7, despite the poor adhesive property of the silver sintering paste 9. As a result, the component 3 is optimally positioned even under process pressure.
  • Extensive "taboo zones” can therefore be dispensed with in the context of a circuit layout and a reduction in area of the entire substrate 5 can be achieved Moreover, elaborate fixings of the component 3 can be dispensed with by means of a punch which is difficult to position and has an impression corresponding to the component 3
  • the stamp 11 shown schematically in FIG. 2 is advantageously designed as a silicone stamp in order to ensure elastic resilience of the flat stamp surface 13.
  • the proposed assembly 1 and the advantageous method significantly increase the process reliability during production and thus ensure series process capability.
  • the bulges 19 may be conditioned by the system.
  • these are also introduced, if this is not the case, to a
  • Substrate 5 of course, any other substrate, such as a stamped grid, are used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Engineering (AREA)
  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)

Abstract

L'invention concerne un module (1) avec un substrat (5) et au moins un composant (3) fixé sur celui-ci par frittage avec un agent de frittage (8), en particulier une pâte de frittage. Conformément à l'invention, l'agent de frittage (8) est disposé dans un renfoncement (7) du substrat (5) recevant au moins en partie le composant (3). En outre, l'invention concerne un procédé de fabrication d'un module avec un substrat et au moins un composant fixé sur celui-ci par frittage avec un agent de frittage, en particulier une pâte de frittage. Conformément à l'invention, l'agent de frittage est introduit dans un renfoncement du substrat recevant au moins en partie le composant.
EP08774783A 2007-08-09 2008-07-04 Module et fabrication d'un tel module Withdrawn EP2179443A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007037538A DE102007037538A1 (de) 2007-08-09 2007-08-09 Baugruppe sowie Herstellung einer Baugruppe
PCT/EP2008/058705 WO2009019091A1 (fr) 2007-08-09 2008-07-04 Module et fabrication d'un tel module

Publications (1)

Publication Number Publication Date
EP2179443A1 true EP2179443A1 (fr) 2010-04-28

Family

ID=39811669

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08774783A Withdrawn EP2179443A1 (fr) 2007-08-09 2008-07-04 Module et fabrication d'un tel module

Country Status (6)

Country Link
US (2) US8552306B2 (fr)
EP (1) EP2179443A1 (fr)
JP (1) JP2010536168A (fr)
CN (1) CN101779285B (fr)
DE (1) DE102007037538A1 (fr)
WO (1) WO2009019091A1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4966261B2 (ja) * 2008-06-30 2012-07-04 ニチコン株式会社 半導体装置およびその製造方法
DE102010038362A1 (de) 2010-07-23 2012-01-26 Robert Bosch Gmbh Kontaktelement
JP6115215B2 (ja) * 2013-03-15 2017-04-19 三菱マテリアル株式会社 パワーモジュール用基板の製造方法及びパワーモジュールの製造方法
WO2014167143A1 (fr) * 2013-04-12 2014-10-16 Nagares, S.A. Dispositif électronique à dissipation thermique intégrée, dispositif de commande électronique et relais statique le comprenant, et procédé de fabrication de ce dispositif
JP2015115481A (ja) * 2013-12-12 2015-06-22 株式会社東芝 半導体部品および半導体部品の製造方法
JP6129107B2 (ja) * 2014-03-27 2017-05-17 三菱電機株式会社 電力用半導体装置、および電力用半導体装置の製造方法
DE102014014473C5 (de) * 2014-09-27 2022-10-27 Audi Ag Verfahren zum Herstellen einer Halbleiteranordnung sowie entsprechende Halbleiteranordnung
US9589864B2 (en) * 2015-05-14 2017-03-07 Qorvo Us, Inc. Substrate with embedded sintered heat spreader and process for making the same
DE102016114963B3 (de) 2016-08-11 2018-01-11 Endress+Hauser Flowtec Ag Sensor für ein thermisches Durchflussmessgerät, ein thermisches Durchflussmessgerät und ein Verfahren zum Herstellen eines Sensors eines thermischen Durchflussmessgeräts
US10906274B2 (en) * 2018-11-14 2021-02-02 Qorvo Us, Inc. Laminate substrate with sintered components
US11626340B2 (en) 2019-12-12 2023-04-11 Qorvo Us, Inc. Integrated circuit (IC) package with embedded heat spreader in a redistribution layer (RDL)
JP7239051B2 (ja) * 2020-03-04 2023-03-14 株式会社デンソー 半導体装置およびその製造方法
US11776871B2 (en) * 2020-12-15 2023-10-03 Semiconductor Components Industries, Llc Module with substrate recess for conductive-bonding component
JPWO2025084247A1 (fr) * 2023-10-19 2025-04-24

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547810A (ja) * 1991-08-09 1993-02-26 Fujitsu Miyagi Electron:Kk リードフレーム
JPH0945814A (ja) * 1995-07-31 1997-02-14 Nec Corp 半導体装置
JP2005101353A (ja) * 2003-09-25 2005-04-14 Toshiba Corp セラミックス回路基板
JP2005136375A (ja) * 2003-10-09 2005-05-26 Hitachi Ltd 電子部品の実装方法，半導体モジュール及び半導体装置
JP2006352080A (ja) * 2005-05-16 2006-12-28 Fuji Electric Holdings Co Ltd 半導体装置の製造方法および半導体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3414065A1 (de) 1984-04-13 1985-12-12 Siemens AG, 1000 Berlin und 8000 München Anordnung bestehend aus mindestens einem auf einem substrat befestigten elektronischen bauelement und verfahren zur herstellung einer derartigen anordnung
GB2195825B (en) * 1986-09-22 1990-01-10 Motorola Inc Integrated circuit package
JPH02246233A (ja) 1989-03-20 1990-10-02 Fujitsu Ltd ダイボンダ
DE4332752A1 (de) * 1993-09-25 1995-03-30 Bosch Gmbh Robert Bauteil und Verfahren zu dessen Herstellung
JPH07221218A (ja) * 1994-02-03 1995-08-18 Toshiba Corp 半導体装置
JP3316714B2 (ja) * 1994-05-31 2002-08-19 三菱電機株式会社 半導体装置
JPH09283544A (ja) 1996-04-10 1997-10-31 Toshiba Corp 半導体装置
SE515856C2 (sv) * 1999-05-19 2001-10-22 Ericsson Telefon Ab L M Bärare för elektronikkomponenter
DE10009678C1 (de) * 2000-02-29 2001-07-19 Siemens Ag Wärmeleitende Klebstoffverbindung und Verfahren zum Herstellen einer wärmeleitenden Klebstoffverbindung
DE10019443A1 (de) * 2000-04-19 2001-10-31 Texas Instruments Deutschland Vorrichtung zum Befestigen eines Halbleiter-Chips auf einem Chip-Träger
DE10062108B4 (de) 2000-12-13 2010-04-15 Infineon Technologies Ag Leistungsmodul mit verbessertem transienten Wärmewiderstand
JP2002353255A (ja) * 2001-05-30 2002-12-06 Moric Co Ltd 半導体チップ半田付け用ランドパターン
TWI257693B (en) * 2003-08-25 2006-07-01 Advanced Semiconductor Eng Leadless package
US20050127134A1 (en) * 2003-09-15 2005-06-16 Guo-Quan Lu Nano-metal composite made by deposition from colloidal suspensions
US7223638B2 (en) 2004-05-13 2007-05-29 Intel Corporation Microelectronic assembly having a thermally conductive member with a cavity to contain a portion of a thermal interface material
US7393771B2 (en) * 2004-06-29 2008-07-01 Hitachi, Ltd. Method for mounting an electronic part on a substrate using a liquid containing metal particles
DE102005047566C5 (de) * 2005-10-05 2011-06-09 Semikron Elektronik Gmbh & Co. Kg Anordnung mit einem Leistungshalbleiterbauelement und mit einem Gehäuse sowie Herstellungsverfahren hierzu
DE102005058794A1 (de) * 2005-12-09 2007-06-14 Semikron Elektronik Gmbh & Co. Kg Vorrichtung und getaktetes Verfahren zur Drucksinterverbindung

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547810A (ja) * 1991-08-09 1993-02-26 Fujitsu Miyagi Electron:Kk リードフレーム
JPH0945814A (ja) * 1995-07-31 1997-02-14 Nec Corp 半導体装置
JP2005101353A (ja) * 2003-09-25 2005-04-14 Toshiba Corp セラミックス回路基板
JP2005136375A (ja) * 2003-10-09 2005-05-26 Hitachi Ltd 電子部品の実装方法，半導体モジュール及び半導体装置
JP2006352080A (ja) * 2005-05-16 2006-12-28 Fuji Electric Holdings Co Ltd 半導体装置の製造方法および半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2009019091A1 *

Also Published As

Publication number Publication date
JP2010536168A (ja) 2010-11-25
US20140001244A1 (en) 2014-01-02
CN101779285A (zh) 2010-07-14
WO2009019091A1 (fr) 2009-02-12
CN101779285B (zh) 2013-01-16
US8552306B2 (en) 2013-10-08
US9233436B2 (en) 2016-01-12
US20100252312A1 (en) 2010-10-07
DE102007037538A1 (de) 2009-02-12

Similar Documents

Publication Publication Date Title
EP2179443A1 (fr) Module et fabrication d'un tel module
EP3103138B1 (fr) Procédé de montage d'un composant électrique en utilisant un capot
DE102010021764B4 (de) Verfahren zur Niedertemperatur Drucksinterverbindung zweier Verbindungspartner
DE10009678C1 (de) Wärmeleitende Klebstoffverbindung und Verfahren zum Herstellen einer wärmeleitenden Klebstoffverbindung
EP3036761B1 (fr) Procédé de soudage par diffusion d'un composant électronique avec une surface de montage avec des enfoncements sur un substrat
DE102014206608A1 (de) Verfahren zum Montieren eines elektrischen Bauelements, bei der eine Haube zum Einsatz kommt, und zur Anwendung in diesem Verfahren geeignete Haube
EP0330895A2 (fr) Procédé pour fixer des composants électroniques sur des substrats et dispositif pour sa réalisation
DE102009000192A1 (de) Sinterwerkstoff, Sinterverbindung sowie Verfahren zum Herstellen eines Sinterverbindung
DE102007047698A1 (de) Vorrichtung und Verfahren zum Verbinden von Komponenten
DE102018207955A1 (de) Leistungselektronisches Metall-Keramik-Modul und Leiterplattenmodul mit integriertem leistungselektronischen Metall-Keramik-Modul sowie Verfahren zu deren Herstellung
DE102012201172A1 (de) Leistungshalbleitermodul mit geprägter Bodenplatte und Verfahren zur Herstellung eines Leistungshalbleitermoduls mit geprägter Bodenplatte
DE102007022337A1 (de) Gesintertes Leistungshalbleitersubstrat sowie Herstellungsverfahren hierzu
EP2847787A1 (fr) Procédé à deux niveaux pour assembler un semi-conducteur sur un substrat avec un matériau de l'iaison à base d'argent
WO2001075963A1 (fr) Procede de realisation d'une liaison thermoconductrice entre deux pieces
DE102017116372B3 (de) Drucksinterverfahren und Druckübertragungseinrichtung hierfür
DE102007021073B4 (de) Verfahren zum Herstellen einer Schaltungsanordnung
DE102011005322B4 (de) Verfahren zur Herstellung eines Leistungshalbleitersubstrates
EP2271196A1 (fr) Procédé de fabrication d'un dispositif de régulation du courant doté d'un dispositif de refroidissement et dispositif de régulation du courant
DE102013200868B4 (de) Verfahren zur Herstellung einer stoffschlüssigen Verbindung und einer elektrischen Verbindung
DE102008055138A1 (de) Hochtemperaturbeständige lötmittelfreie Bauelementstruktur und Verfahren zum elektrischen Kontaktieren
DE102015107712B3 (de) Verfahren zur Herstellung eines Schaltungsträgers
DE102014206606A1 (de) Verfahren zum Montieren eines elektrischen Bauelements auf einem Substrat
DE102007022338B4 (de) Herstellungsverfahren für ein Leistungshalbleiterbauelement mit Metallkontaktschicht
DE10142975B4 (de) Wärmeableitelement für elktronische Bauteile und Verfahren zum Anbringen desselben
WO2008071576A2 (fr) Ensemble de circuits et procédé de production d'un ensemble de circuits

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20100309

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA MK RS

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20101129

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ROBERT BOSCH GMBH

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20200603