EP2529312A4 - Interface methods and apparatus for memory devices - Google Patents

Interface methods and apparatus for memory devices

Info

Publication number
EP2529312A4
EP2529312A4 EP11737662.4A EP11737662A EP2529312A4 EP 2529312 A4 EP2529312 A4 EP 2529312A4 EP 11737662 A EP11737662 A EP 11737662A EP 2529312 A4 EP2529312 A4 EP 2529312A4
Authority
EP
European Patent Office
Prior art keywords
memory
memory devices
request
interface methods
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11737662.4A
Other languages
German (de)
French (fr)
Other versions
EP2529312A2 (en
Inventor
Naveen Muralimanohar
Norman Paul Jouppi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Enterprise Development LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of EP2529312A2 publication Critical patent/EP2529312A2/en
Publication of EP2529312A4 publication Critical patent/EP2529312A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Dram (AREA)

Abstract

A disclosed example apparatus includes an interface (702, 726) to receive a request to access a memory (602a) of a memory module (600) and a data store status monitor (730) to determine a status of the memory. The example apparatus also includes a message output subsystem (732) to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.
EP11737662.4A 2010-01-28 2011-01-27 Interface methods and apparatus for memory devices Withdrawn EP2529312A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29915810P 2010-01-28 2010-01-28
PCT/US2011/022762 WO2011094436A2 (en) 2010-01-28 2011-01-27 Interface methods and apparatus for memory devices

Publications (2)

Publication Number Publication Date
EP2529312A2 EP2529312A2 (en) 2012-12-05
EP2529312A4 true EP2529312A4 (en) 2013-07-03

Family

ID=44320123

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11737662.4A Withdrawn EP2529312A4 (en) 2010-01-28 2011-01-27 Interface methods and apparatus for memory devices

Country Status (3)

Country Link
EP (1) EP2529312A4 (en)
CN (1) CN102576338B (en)
WO (1) WO2011094436A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8938589B2 (en) 2010-01-28 2015-01-20 Hewlett-Packard Development Company, L. P. Interface methods and apparatus for memory devices using arbitration
EP2529374A4 (en) 2010-01-28 2014-04-02 Hewlett Packard Development Co MEMORY ACCESS METHODS AND APPARATUS
KR101366967B1 (en) * 2012-06-12 2014-02-25 엘에스산전 주식회사 A circuit for memory sharing
US9116856B2 (en) * 2012-11-08 2015-08-25 Qualcomm Incorporated Intelligent dual data rate (DDR) memory controller
US9411774B2 (en) * 2013-04-23 2016-08-09 Arm Limited Memory access control
US9324397B1 (en) * 2015-01-16 2016-04-26 Qualcomm Incorporated Common die for supporting different external memory types with minimal packaging complexity
US10402349B2 (en) * 2017-02-08 2019-09-03 Arm Limited Memory controller having data access hint message for specifying the given range of one or more memory addresses

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718770A1 (en) * 1994-12-20 1996-06-26 Motorola, Inc. Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous
US6052772A (en) * 1998-04-13 2000-04-18 International Business Machines Corporation Memory request protocol method
US6523098B1 (en) * 1999-12-22 2003-02-18 Intel Corporation Mechanism for efficient low priority write draining
US20080005479A1 (en) * 2006-05-22 2008-01-03 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6360285B1 (en) * 1994-06-30 2002-03-19 Compaq Computer Corporation Apparatus for determining memory bank availability in a computer system
US7020741B1 (en) * 2003-04-29 2006-03-28 Advanced Micro Devices, Inc. Apparatus and method for isochronous arbitration to schedule memory refresh requests
US7213082B2 (en) * 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
US7426613B2 (en) * 2005-06-16 2008-09-16 Lexmark International, Inc. Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718770A1 (en) * 1994-12-20 1996-06-26 Motorola, Inc. Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous
US6052772A (en) * 1998-04-13 2000-04-18 International Business Machines Corporation Memory request protocol method
US6523098B1 (en) * 1999-12-22 2003-02-18 Intel Corporation Mechanism for efficient low priority write draining
US20080005479A1 (en) * 2006-05-22 2008-01-03 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2011094436A2 *

Also Published As

Publication number Publication date
CN102576338B (en) 2015-06-10
WO2011094436A3 (en) 2011-11-24
WO2011094436A2 (en) 2011-08-04
EP2529312A2 (en) 2012-12-05
CN102576338A (en) 2012-07-11

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Effective date: 20130531

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 12/08 20060101ALI20130524BHEP

Ipc: G06F 12/00 20060101ALI20130524BHEP

Ipc: G06F 13/38 20060101ALI20130524BHEP

Ipc: G06F 13/16 20060101AFI20130524BHEP

Ipc: G11C 7/00 20060101ALI20130524BHEP

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: HEWLETT PACKARD ENTERPRISE DEVELOPMENT L.P.

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