EP2718780A4 - NON-DEFORMATION CLOCK DIVIDER APPARATUS WITH FAST CLOCK CHANGE, AND METHOD THEREOF - Google Patents

NON-DEFORMATION CLOCK DIVIDER APPARATUS WITH FAST CLOCK CHANGE, AND METHOD THEREOF

Info

Publication number
EP2718780A4
EP2718780A4 EP11867485.2A EP11867485A EP2718780A4 EP 2718780 A4 EP2718780 A4 EP 2718780A4 EP 11867485 A EP11867485 A EP 11867485A EP 2718780 A4 EP2718780 A4 EP 2718780A4
Authority
EP
European Patent Office
Prior art keywords
deformation
clock
change
divider apparatus
fast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP11867485.2A
Other languages
German (de)
French (fr)
Other versions
EP2718780A1 (en
Inventor
Ari Hatula
Jussi Pennala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Technologies Oy
Original Assignee
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Inc filed Critical Nokia Inc
Publication of EP2718780A1 publication Critical patent/EP2718780A1/en
Publication of EP2718780A4 publication Critical patent/EP2718780A4/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
EP11867485.2A 2011-06-09 2011-06-09 NON-DEFORMATION CLOCK DIVIDER APPARATUS WITH FAST CLOCK CHANGE, AND METHOD THEREOF Ceased EP2718780A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/FI2011/050538 WO2012168533A1 (en) 2011-06-09 2011-06-09 Apparatus for glitchless clock divider with fast clock change and method thereof

Publications (2)

Publication Number Publication Date
EP2718780A1 EP2718780A1 (en) 2014-04-16
EP2718780A4 true EP2718780A4 (en) 2015-02-25

Family

ID=47295538

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11867485.2A Ceased EP2718780A4 (en) 2011-06-09 2011-06-09 NON-DEFORMATION CLOCK DIVIDER APPARATUS WITH FAST CLOCK CHANGE, AND METHOD THEREOF

Country Status (2)

Country Link
EP (1) EP2718780A4 (en)
WO (1) WO2012168533A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9397667B2 (en) 2014-09-04 2016-07-19 Texas Instruments Deutschland Gmbh Shared divide by N clock divider
CN105138069B (en) * 2015-10-23 2018-03-09 上海华力创通半导体有限公司 A kind of numeric field clock selecting device and implementation method
US9698781B1 (en) * 2016-05-26 2017-07-04 Intel Corporation Dynamic clock gating frequency scaling
US10606305B2 (en) * 2018-04-30 2020-03-31 Qualcomm Incorporated Processor load step balancing
CN111092618A (en) * 2019-12-23 2020-05-01 珠海全志科技股份有限公司 Frequency adjusting method and device of system-on-chip frequency modulation equipment
US11874693B2 (en) 2022-05-24 2024-01-16 Analog Devices International Unlimited Company Reconfigurable clock divider

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825662A (en) * 1995-08-18 1998-10-20 Xilinx, Inc. Computer-implemented method of optimizing a time multiplexed programmable logic device
US6055644A (en) * 1997-05-30 2000-04-25 Hewlett-Packard Company Multi-channel architecture with channel independent clock signals
WO2010070830A1 (en) * 2008-12-17 2010-06-24 日本電気株式会社 Clock frequency divider circuit and clock frequency dividing method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2228598A (en) * 1989-02-28 1990-08-29 Ibm Clock signal generator for a data processing system
JP2003216268A (en) * 2002-01-28 2003-07-31 Nec Microsystems Ltd Circuit and method for selecting clock
US7328229B2 (en) 2003-01-10 2008-02-05 Texas Instruments Incorporated Clock divider with glitch free dynamic divide-by change
EP1895380A1 (en) * 2006-09-04 2008-03-05 Digi International Inc. Dynamic clock change circuit
JP4790060B2 (en) * 2007-03-20 2011-10-12 富士通セミコンダクター株式会社 Clock signal selection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825662A (en) * 1995-08-18 1998-10-20 Xilinx, Inc. Computer-implemented method of optimizing a time multiplexed programmable logic device
US6055644A (en) * 1997-05-30 2000-04-25 Hewlett-Packard Company Multi-channel architecture with channel independent clock signals
WO2010070830A1 (en) * 2008-12-17 2010-06-24 日本電気株式会社 Clock frequency divider circuit and clock frequency dividing method
US20110222644A1 (en) * 2008-12-17 2011-09-15 Atsufumi Shibayama Clock frequency divider circuit and clock frequency division method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KMPAN SHI ET AL: "Hierarchical timing closure methodology for OMAP: an open multimedia application platform", ASIC, 2003. PROCEEDINGS. 5TH INTERNATIONAL CONFERENCE ON OCT. 21-24, 2003, PISCATAWAY, NJ, USA,IEEE, vol. 1, 21 October 2003 (2003-10-21), pages 238 - 241, XP010690613, ISBN: 978-0-7803-7889-6 *
See also references of WO2012168533A1 *

Also Published As

Publication number Publication date
EP2718780A1 (en) 2014-04-16
WO2012168533A1 (en) 2012-12-13

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