EP3218930A4 - Package for electronic system having semiconductor chips - Google Patents

Package for electronic system having semiconductor chips Download PDF

Info

Publication number
EP3218930A4
EP3218930A4 EP15859853.2A EP15859853A EP3218930A4 EP 3218930 A4 EP3218930 A4 EP 3218930A4 EP 15859853 A EP15859853 A EP 15859853A EP 3218930 A4 EP3218930 A4 EP 3218930A4
Authority
EP
European Patent Office
Prior art keywords
package
semiconductor chips
electronic system
chips
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP15859853.2A
Other languages
German (de)
French (fr)
Other versions
EP3218930B1 (en
EP3218930A1 (en
Inventor
Osvaldo Jorge Lopez
Jonathan Almeria Noquil
Thomas Eugene Grebs
Simon John Molloy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of EP3218930A1 publication Critical patent/EP3218930A1/en
Publication of EP3218930A4 publication Critical patent/EP3218930A4/en
Application granted granted Critical
Publication of EP3218930B1 publication Critical patent/EP3218930B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/658—Shapes or dispositions of interconnections for devices provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/074—Connecting or disconnecting of anisotropic conductive adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
EP15859853.2A 2014-11-11 2015-11-11 Package for electronic system having semiconductor chips Active EP3218930B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/537,943 US9305852B1 (en) 2014-11-11 2014-11-11 Silicon package for embedded electronic system having stacked semiconductor chips
PCT/US2015/060208 WO2016077488A1 (en) 2014-11-11 2015-11-11 Package for electronic system having semiconductor chips

Publications (3)

Publication Number Publication Date
EP3218930A1 EP3218930A1 (en) 2017-09-20
EP3218930A4 true EP3218930A4 (en) 2018-07-25
EP3218930B1 EP3218930B1 (en) 2020-05-27

Family

ID=55589080

Family Applications (1)

Application Number Title Priority Date Filing Date
EP15859853.2A Active EP3218930B1 (en) 2014-11-11 2015-11-11 Package for electronic system having semiconductor chips

Country Status (5)

Country Link
US (2) US9305852B1 (en)
EP (1) EP3218930B1 (en)
JP (1) JP6709785B2 (en)
CN (1) CN107078124B (en)
WO (1) WO2016077488A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9893058B2 (en) * 2015-09-17 2018-02-13 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor device having reduced on-state resistance and structure
EP3279935B1 (en) * 2016-08-02 2019-01-02 ABB Schweiz AG Power semiconductor module
US20200235067A1 (en) * 2019-01-22 2020-07-23 Texas Instruments Incorporated Electronic device flip chip package with exposed clip
US11031321B2 (en) * 2019-03-15 2021-06-08 Infineon Technologies Ag Semiconductor device having a die pad with a dam-like configuration
US11024564B2 (en) 2019-06-19 2021-06-01 Texas Instruments Incorporated Packaged electronic device with film isolated power stack
EP3944304A1 (en) * 2020-07-20 2022-01-26 Nexperia B.V. A semiconductor device and a method of manufacture
CN114899171B (en) * 2022-04-29 2025-10-03 佛山市国星光电股份有限公司 A wire-free power device
CN115188853A (en) * 2022-08-15 2022-10-14 西安西热产品认证检测有限公司 A low temperature double-sided photovoltaic module

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004128356A (en) * 2002-10-04 2004-04-22 Fujitsu Ltd Semiconductor device
EP1501126A1 (en) * 2003-11-05 2005-01-26 Infineon Technologies AG Semiconductor chip having a cavity for stacked die application
US20090189291A1 (en) * 2008-01-24 2009-07-30 Infineon Technologies Ag Multi-chip module
US20100301496A1 (en) * 2009-05-28 2010-12-02 Texas Instruments Incorporated Structure and Method for Power Field Effect Transistor
US20120104623A1 (en) * 2010-10-28 2012-05-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stepped Interposer for Stacking and Electrically Connecting Semiconductor Die
US20120146177A1 (en) * 2010-12-09 2012-06-14 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Recesses in Substrate for Same Size or Different Sized Die with Vertical Integration
US20140273344A1 (en) * 2013-03-14 2014-09-18 Vishay-Siliconix Method for fabricating stack die package

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568958A (en) * 1984-01-03 1986-02-04 General Electric Company Inversion-mode insulated-gate gallium arsenide field-effect transistors
US7279786B2 (en) * 2005-02-04 2007-10-09 Stats Chippac Ltd. Nested integrated circuit package on package system
WO2012021310A1 (en) * 2010-08-09 2012-02-16 Rambus Inc. Disaggregated semiconductor chip assembly and packaging technique
US8666505B2 (en) * 2010-10-26 2014-03-04 Medtronic, Inc. Wafer-scale package including power source
CN102169872B (en) * 2011-01-26 2013-07-03 上海腾怡半导体有限公司 Power module of integrated inductor
GB2492551A (en) * 2011-07-04 2013-01-09 Accuric Ltd Current regulator
JP2014209091A (en) * 2013-03-25 2014-11-06 ローム株式会社 Semiconductor device
TWI518844B (en) * 2013-12-11 2016-01-21 矽品精密工業股份有限公司 Package structure and its manufacturing method
CN105575913B (en) * 2016-02-23 2019-02-01 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out 3D package structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004128356A (en) * 2002-10-04 2004-04-22 Fujitsu Ltd Semiconductor device
EP1501126A1 (en) * 2003-11-05 2005-01-26 Infineon Technologies AG Semiconductor chip having a cavity for stacked die application
US20090189291A1 (en) * 2008-01-24 2009-07-30 Infineon Technologies Ag Multi-chip module
US20100301496A1 (en) * 2009-05-28 2010-12-02 Texas Instruments Incorporated Structure and Method for Power Field Effect Transistor
US20120104623A1 (en) * 2010-10-28 2012-05-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stepped Interposer for Stacking and Electrically Connecting Semiconductor Die
US20120146177A1 (en) * 2010-12-09 2012-06-14 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Recesses in Substrate for Same Size or Different Sized Die with Vertical Integration
US20140273344A1 (en) * 2013-03-14 2014-09-18 Vishay-Siliconix Method for fabricating stack die package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2016077488A1 *

Also Published As

Publication number Publication date
CN107078124B (en) 2020-11-06
US9305852B1 (en) 2016-04-05
WO2016077488A1 (en) 2016-05-19
EP3218930B1 (en) 2020-05-27
JP6709785B2 (en) 2020-06-17
US20160172338A1 (en) 2016-06-16
CN107078124A (en) 2017-08-18
US10109614B2 (en) 2018-10-23
JP2017535960A (en) 2017-11-30
EP3218930A1 (en) 2017-09-20

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