FI932024L - Foerfarande foer aostadkommande av kontrollerade utskiljningsprofiler i kieselskivor - Google Patents

Foerfarande foer aostadkommande av kontrollerade utskiljningsprofiler i kieselskivor Download PDF

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Publication number
FI932024L
FI932024L FI932024A FI932024A FI932024L FI 932024 L FI932024 L FI 932024L FI 932024 A FI932024 A FI 932024A FI 932024 A FI932024 A FI 932024A FI 932024 L FI932024 L FI 932024L
Authority
FI
Finland
Prior art keywords
utskiljningsprofiler
kontrolerade
kieselskivor
foerfarande foer
foer aostadkommande
Prior art date
Application number
FI932024A
Other languages
English (en)
Finnish (fi)
Other versions
FI932024A7 (fi
FI932024A0 (fi
Inventor
Robert Falster
Giancarlo Ferrero
Graham Fisher
Massimiliano Olmo
Marco Pagani
Original Assignee
Memc Electronic Materials
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials filed Critical Memc Electronic Materials
Publication of FI932024A0 publication Critical patent/FI932024A0/fi
Publication of FI932024A7 publication Critical patent/FI932024A7/fi
Publication of FI932024L publication Critical patent/FI932024L/fi

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
FI932024A 1990-11-15 1991-11-11 Foerfarande foer aostadkommande av kontrollerade utskiljningsprofiler i kieselskivor FI932024L (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT48481A IT1242014B (it) 1990-11-15 1990-11-15 Procedimento per il trattamento di fette di silicio per ottenere in esse profili di precipitazione controllati per la produzione di componenti elettronici.
PCT/IT1991/000095 WO1992009101A1 (en) 1990-11-15 1991-11-11 Process for achieving controlled precipitation profiles in silicon wafers

Publications (3)

Publication Number Publication Date
FI932024A0 FI932024A0 (fi) 1993-05-05
FI932024A7 FI932024A7 (fi) 1993-06-29
FI932024L true FI932024L (fi) 1993-06-29

Family

ID=11266818

Family Applications (1)

Application Number Title Priority Date Filing Date
FI932024A FI932024L (fi) 1990-11-15 1991-11-11 Foerfarande foer aostadkommande av kontrollerade utskiljningsprofiler i kieselskivor

Country Status (17)

Country Link
US (1) US5403406A (de)
EP (1) EP0557415B1 (de)
JP (2) JP3412636B2 (de)
KR (1) KR100247464B1 (de)
AT (1) ATE176084T1 (de)
AU (1) AU9033591A (de)
CZ (1) CZ84993A3 (de)
DE (1) DE69130802T2 (de)
FI (1) FI932024L (de)
IL (1) IL99979A (de)
IT (1) IT1242014B (de)
MY (1) MY110258A (de)
SG (1) SG64901A1 (de)
SK (1) SK47093A3 (de)
TW (1) TW205110B (de)
WO (1) WO1992009101A1 (de)
ZA (1) ZA918831B (de)

Families Citing this family (48)

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JPH0574782A (ja) * 1991-09-10 1993-03-26 Mitsubishi Materials Corp シリコン基板の製造方法
JPH0684925A (ja) * 1992-07-17 1994-03-25 Toshiba Corp 半導体基板およびその処理方法
JP2874834B2 (ja) * 1994-07-29 1999-03-24 三菱マテリアル株式会社 シリコンウェーハのイントリンシックゲッタリング処理法
US5788763A (en) * 1995-03-09 1998-08-04 Toshiba Ceramics Co., Ltd. Manufacturing method of a silicon wafer having a controlled BMD concentration
US5593494A (en) * 1995-03-14 1997-01-14 Memc Electronic Materials, Inc. Precision controlled precipitation of oxygen in silicon
US6485807B1 (en) 1997-02-13 2002-11-26 Samsung Electronics Co., Ltd. Silicon wafers having controlled distribution of defects, and methods of preparing the same
SG64470A1 (en) 1997-02-13 1999-04-27 Samsung Electronics Co Ltd Methods of manufacturing monocrystalline silicon ingots and wafers by controlling pull rate profiles in a hot zone furnace and ingots and wafers manufactured thereby
US6503594B2 (en) 1997-02-13 2003-01-07 Samsung Electronics Co., Ltd. Silicon wafers having controlled distribution of defects and slip
US5994761A (en) 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6190631B1 (en) 1997-04-09 2001-02-20 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
TW429478B (en) * 1997-08-29 2001-04-11 Toshiba Corp Semiconductor device and method for manufacturing the same
US5882989A (en) * 1997-09-22 1999-03-16 Memc Electronic Materials, Inc. Process for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
US6340392B1 (en) 1997-10-24 2002-01-22 Samsung Electronics Co., Ltd. Pulling methods for manufacturing monocrystalline silicone ingots by controlling temperature at the center and edge of an ingot-melt interface
JPH11150119A (ja) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp シリコン半導体基板の熱処理方法とその装置
JP3746153B2 (ja) * 1998-06-09 2006-02-15 信越半導体株式会社 シリコンウエーハの熱処理方法
US6828690B1 (en) * 1998-08-05 2004-12-07 Memc Electronic Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
EP1114454A2 (de) * 1998-09-02 2001-07-11 MEMC Electronic Materials, Inc. Silizium auf isolator struktur aus einem einkristallsilizium mit niedriger fehlerdichte
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
US6191010B1 (en) * 1998-09-02 2001-02-20 Memc Electronic Materials, Inc. Process for preparing an ideal oxygen precipitating silicon wafer
JP4405082B2 (ja) 1998-09-02 2010-01-27 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 内部ゲッタリング性の改良された熱アニーリングされたウエハ
US6416836B1 (en) 1998-10-14 2002-07-09 Memc Electronic Materials, Inc. Thermally annealed, low defect density single crystal silicon
JP2000154070A (ja) * 1998-11-16 2000-06-06 Suminoe Textile Co Ltd セラミックス三次元構造体及びその製造方法
US6284384B1 (en) 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
DE19924649B4 (de) * 1999-05-28 2004-08-05 Siltronic Ag Halbleiterscheiben mit Kristallgitter-Defekten und Verfahren zur Herstellung derselben
US20030051656A1 (en) 1999-06-14 2003-03-20 Charles Chiun-Chieh Yang Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
KR100378184B1 (ko) * 1999-11-13 2003-03-29 삼성전자주식회사 제어된 결함 분포를 갖는 실리콘 웨이퍼, 그의 제조공정및 단결정 실리콘 잉곳의 제조를 위한 초크랄스키 풀러
JP2001308101A (ja) * 2000-04-19 2001-11-02 Mitsubishi Materials Silicon Corp シリコンウェーハの熱処理方法及びシリコンウェーハ
DE10024710A1 (de) * 2000-05-18 2001-12-20 Steag Rtp Systems Gmbh Einstellung von Defektprofilen in Kristallen oder kristallähnlichen Strukturen
EP1295324A1 (de) * 2000-06-30 2003-03-26 MEMC Electronic Materials, Inc. Verfahren und vorrichtung zur herstellung eines siliziumwafers mit einer defektfreien zone
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
JP4055343B2 (ja) * 2000-09-26 2008-03-05 株式会社Ｓｕｍｃｏ シリコン半導体基板の熱処理方法
JP4106862B2 (ja) 2000-10-25 2008-06-25 信越半導体株式会社 シリコンウェーハの製造方法
JP2004537161A (ja) * 2001-04-11 2004-12-09 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 高抵抗率ｃｚシリコンにおけるサーマルドナー生成の制御
TW541581B (en) * 2001-04-20 2003-07-11 Memc Electronic Materials Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
US7883628B2 (en) * 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
US7749910B2 (en) * 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
JP4567251B2 (ja) * 2001-09-14 2010-10-20 シルトロニック・ジャパン株式会社 シリコン半導体基板およびその製造方法
US6955718B2 (en) * 2003-07-08 2005-10-18 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
JP2005051040A (ja) * 2003-07-29 2005-02-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及び半導体基板
KR100531552B1 (ko) * 2003-09-05 2005-11-28 주식회사 하이닉스반도체 실리콘 웨이퍼 및 그 제조방법
US7485928B2 (en) * 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US20090004426A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates
JP2009177194A (ja) * 2009-03-19 2009-08-06 Sumco Corp シリコンウェーハの製造方法、シリコンウェーハ
JP7110204B2 (ja) * 2016-12-28 2022-08-01 サンエディソン・セミコンダクター・リミテッド イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法

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JPS56158431A (en) * 1980-05-13 1981-12-07 Meidensha Electric Mfg Co Ltd Forming of oxidized film of semiconductor element for electric power
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Also Published As

Publication number Publication date
EP0557415A1 (de) 1993-09-01
DE69130802D1 (de) 1999-03-04
KR100247464B1 (ko) 2000-03-15
JP3412636B2 (ja) 2003-06-03
FI932024A7 (fi) 1993-06-29
ZA918831B (en) 1992-08-26
AU9033591A (en) 1992-06-11
IT9048481A0 (it) 1990-11-15
IL99979A0 (en) 1992-08-18
SG64901A1 (en) 1999-05-25
EP0557415B1 (de) 1999-01-20
JPH06504878A (ja) 1994-06-02
IL99979A (en) 1995-07-31
ATE176084T1 (de) 1999-02-15
TW205110B (de) 1993-05-01
IT9048481A1 (it) 1992-05-15
DE69130802T2 (de) 1999-08-19
IT1242014B (it) 1994-02-02
JP2003243402A (ja) 2003-08-29
FI932024A0 (fi) 1993-05-05
CZ84993A3 (en) 1993-11-17
MY110258A (en) 1998-03-31
WO1992009101A1 (en) 1992-05-29
SK47093A3 (en) 1993-08-11
US5403406A (en) 1995-04-04

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