FR2563656B1 - Bloc de circuits a integration a grande echelle - Google Patents

Bloc de circuits a integration a grande echelle

Info

Publication number
FR2563656B1
FR2563656B1 FR8506423A FR8506423A FR2563656B1 FR 2563656 B1 FR2563656 B1 FR 2563656B1 FR 8506423 A FR8506423 A FR 8506423A FR 8506423 A FR8506423 A FR 8506423A FR 2563656 B1 FR2563656 B1 FR 2563656B1
Authority
FR
France
Prior art keywords
circuit block
integration circuit
scale integration
scale
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8506423A
Other languages
English (en)
Other versions
FR2563656A1 (fr
Inventor
Mitsuru Nitta
Tatsuo Satoh
Tatsuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59083810A external-priority patent/JPS60229344A/ja
Priority claimed from JP59247123A external-priority patent/JPS61125196A/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2563656A1 publication Critical patent/FR2563656A1/fr
Application granted granted Critical
Publication of FR2563656B1 publication Critical patent/FR2563656B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
FR8506423A 1984-04-27 1985-04-26 Bloc de circuits a integration a grande echelle Expired FR2563656B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59083810A JPS60229344A (ja) 1984-04-27 1984-04-27 ボンデイング方法
JP59247123A JPS61125196A (ja) 1984-11-22 1984-11-22 回路基板

Publications (2)

Publication Number Publication Date
FR2563656A1 FR2563656A1 (fr) 1985-10-31
FR2563656B1 true FR2563656B1 (fr) 1987-05-15

Family

ID=26424853

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8506423A Expired FR2563656B1 (fr) 1984-04-27 1985-04-26 Bloc de circuits a integration a grande echelle

Country Status (2)

Country Link
US (1) US4754371A (fr)
FR (1) FR2563656B1 (fr)

Families Citing this family (35)

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JPS62108593A (ja) * 1985-11-06 1987-05-19 日本電気株式会社 多層配線基板
US5066831A (en) * 1987-10-23 1991-11-19 Honeywell Inc. Universal semiconductor chip package
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components
US5159536A (en) * 1988-05-13 1992-10-27 Mupac Corporation Panel board
US4916259A (en) * 1988-08-01 1990-04-10 International Business Machines Corporation Composite dielectric structure for optimizing electrical performance in high performance chip support packages
JPH0268571A (ja) * 1988-09-02 1990-03-08 Konica Corp 画像形成装置に於けるプリント基板
KR930010076B1 (ko) * 1989-01-14 1993-10-14 티디케이 가부시키가이샤 다층혼성집적회로
JP2790640B2 (ja) * 1989-01-14 1998-08-27 ティーディーケイ株式会社 混成集積回路部品の構造
US5072075A (en) * 1989-06-28 1991-12-10 Digital Equipment Corporation Double-sided hybrid high density circuit board and method of making same
JP3090453B2 (ja) * 1989-07-10 2000-09-18 株式会社日立製作所 厚膜薄膜積層基板およびそれを用いた電子回路装置
JPH0378290A (ja) * 1989-08-21 1991-04-03 Hitachi Ltd 多層配線基板
US5061824A (en) * 1989-08-23 1991-10-29 Ncr Corporation Backpanel having multiple logic family signal layers
US5036163A (en) * 1989-10-13 1991-07-30 Honeywell Inc. Universal semiconductor chip package
US5067004A (en) * 1989-12-13 1991-11-19 Digital Equipment Corporation Module for interconnecting integrated circuits
MY105486A (en) * 1989-12-15 1994-10-31 Tdk Corp A multilayer hybrid circuit.
GB9000264D0 (en) * 1990-01-05 1990-03-07 Int Computers Ltd Circuit packaging
JPH0716100B2 (ja) * 1990-01-10 1995-02-22 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層配線モジュール
US5157477A (en) * 1990-01-10 1992-10-20 International Business Machines Corporation Matched impedance vertical conductors in multilevel dielectric laminated wiring
JP2996510B2 (ja) * 1990-11-30 2000-01-11 株式会社日立製作所 電子回路基板
DE69210329T2 (de) * 1991-07-25 1996-11-28 Ncr Int Inc Mehrschichtiger Träger für integrierte Schaltungen und Verfahren zu dessen Herstellung
US5239448A (en) * 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
JPH07123150B2 (ja) * 1992-03-06 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション ハイブリッド半導体モジュール
DE69300506T2 (de) * 1992-04-06 1996-04-04 Nippon Electric Co Herstellungsverfahren von mehrlagigen keramischen Substraten.
KR950012658B1 (ko) * 1992-07-24 1995-10-19 삼성전자주식회사 반도체 칩 실장방법 및 기판 구조체
US5508938A (en) * 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
US5285018A (en) * 1992-10-02 1994-02-08 International Business Machines Corporation Power and signal distribution in electronic packaging
US5442225A (en) * 1993-08-13 1995-08-15 Lsi Logic Corporation Integrated circuit having interconnects with ringing suppressing elements
JP4127433B2 (ja) * 1998-09-17 2008-07-30 イビデン株式会社 多層ビルドアップ配線板及び多層ビルドアップ配線板の製造方法
KR20080024239A (ko) * 1998-09-17 2008-03-17 이비덴 가부시키가이샤 다층빌드업배선판
US6181004B1 (en) * 1999-01-22 2001-01-30 Jerry D. Koontz Digital signal processing assembly and test method
US8569142B2 (en) * 2003-11-28 2013-10-29 Blackberry Limited Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same
US7649252B2 (en) * 2003-12-26 2010-01-19 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate
DE102004033251B3 (de) 2004-07-08 2006-03-09 Vishay Bccomponents Beyschlag Gmbh Schmelzsicherung für einem Chip
US7518236B2 (en) * 2005-10-26 2009-04-14 General Electric Company Power circuit package and fabrication method
US9069121B2 (en) 2011-07-08 2015-06-30 Nora LIGORANO Fiber optic tapestry

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1167162B (de) * 1961-05-16 1964-04-02 Siemens Ag Lot zum Verloeten von Teilen, von denen eines Gold enthaelt, und Verfahren zum Loeten mit diesem Lot
US3579312A (en) * 1967-03-28 1971-05-18 Du Pont Printed circuits from nonmigrating solders
US3472653A (en) * 1967-03-28 1969-10-14 Du Pont Nonmigrating solders and printed circuits therefrom
FR1552207A (fr) * 1967-11-22 1969-01-03
US3519890A (en) * 1968-04-01 1970-07-07 North American Rockwell Low stress lead
US3742597A (en) * 1971-03-17 1973-07-03 Hadco Printed Circuits Inc Method for making a coated printed circuit board
US3740678A (en) * 1971-03-19 1973-06-19 Ibm Strip transmission line structures
US3855693A (en) * 1973-04-18 1974-12-24 Honeywell Inf Systems Method for assembling microelectronic apparatus
JPS5377857A (en) * 1976-12-22 1978-07-10 Hitachi Ltd Solder material
US4176443A (en) * 1977-03-08 1979-12-04 Sgs-Ates Componenti Elettronici S.P.A. Method of connecting semiconductor structure to external circuits
JPS55130198A (en) * 1979-03-30 1980-10-08 Hitachi Ltd Hybrid integrated circuit board for tuner
DE2940593A1 (de) * 1979-10-06 1981-04-16 Ibm Deutschland Gmbh, 7000 Stuttgart Mehrlagen-modul mit konstantem wellenwiderstand
US4322778A (en) * 1980-01-25 1982-03-30 International Business Machines Corp. High performance semiconductor package assembly
US4396140A (en) * 1981-01-27 1983-08-02 Bell Telephone Laboratories, Incorporated Method of bonding electronic components
JPS5815264A (ja) * 1981-07-21 1983-01-28 Nec Corp マルチチツプパツケ−ジ
JPS58100993A (ja) * 1981-12-10 1983-06-15 Tokuriki Honten Co Ltd 金一錫共晶型合金ろう材の製造方法
US4489364A (en) * 1981-12-31 1984-12-18 International Business Machines Corporation Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface
US4498122A (en) * 1982-12-29 1985-02-05 At&T Bell Laboratories High-speed, high pin-out LSI chip package
US4648179A (en) * 1983-06-30 1987-03-10 International Business Machines Corporation Process of making interconnection structure for semiconductor device

Also Published As

Publication number Publication date
US4754371A (en) 1988-06-28
FR2563656A1 (fr) 1985-10-31

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Legal Events

Date Code Title Description
ST Notification of lapse