FR2704689B1 - Procede de formation de motif fin dans un dispositif a semi-conducteur. - Google Patents

Procede de formation de motif fin dans un dispositif a semi-conducteur.

Info

Publication number
FR2704689B1
FR2704689B1 FR9404503A FR9404503A FR2704689B1 FR 2704689 B1 FR2704689 B1 FR 2704689B1 FR 9404503 A FR9404503 A FR 9404503A FR 9404503 A FR9404503 A FR 9404503A FR 2704689 B1 FR2704689 B1 FR 2704689B1
Authority
FR
France
Prior art keywords
forming
semiconductor device
fine pattern
fine
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR9404503A
Other languages
English (en)
Other versions
FR2704689A1 (fr
Inventor
Lee Kang-Hyun
Hong Jong-Seo
Kim Hyoung-Sub
Kim Jae-Jo
Han Min-Seog
Hong Jung-In
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2704689A1 publication Critical patent/FR2704689A1/fr
Application granted granted Critical
Publication of FR2704689B1 publication Critical patent/FR2704689B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/043—Manufacture or treatment of capacitors having no potential barriers using patterning processes to form electrode extensions, e.g. etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
FR9404503A 1993-04-15 1994-04-15 Procede de formation de motif fin dans un dispositif a semi-conducteur. Expired - Lifetime FR2704689B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930006337A KR960006822B1 (ko) 1993-04-15 1993-04-15 반도체장치의 미세패턴 형성방법

Publications (2)

Publication Number Publication Date
FR2704689A1 FR2704689A1 (fr) 1994-11-04
FR2704689B1 true FR2704689B1 (fr) 1995-09-15

Family

ID=19353990

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9404503A Expired - Lifetime FR2704689B1 (fr) 1993-04-15 1994-04-15 Procede de formation de motif fin dans un dispositif a semi-conducteur.

Country Status (5)

Country Link
US (1) US5476807A (fr)
JP (1) JPH06326061A (fr)
KR (1) KR960006822B1 (fr)
DE (1) DE4413152B4 (fr)
FR (1) FR2704689B1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1202331A3 (fr) * 1995-02-28 2002-07-31 Micron Technology, Inc. Procédé de formation d' une structure par redéposition
KR0155831B1 (ko) * 1995-06-20 1998-12-01 김광호 셀프얼라인을 이용한 듀얼패드셀 반도체장치 및 그것의 제조방법
JPH09129612A (ja) * 1995-10-26 1997-05-16 Tokyo Electron Ltd エッチングガス及びエッチング方法
KR100207462B1 (ko) * 1996-02-26 1999-07-15 윤종용 반도체 장치의 커패시터 제조방법
JP2790110B2 (ja) * 1996-02-28 1998-08-27 日本電気株式会社 半導体装置の製造方法
US5731217A (en) * 1996-10-08 1998-03-24 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a filled upper transistor substrate and interconnection thereto
DE19646208C2 (de) * 1996-11-08 2001-08-30 Infineon Technologies Ag Verfahren zur Herstellung eines Kondensators und Speicherfeld
US5879985A (en) * 1997-03-26 1999-03-09 International Business Machines Corporation Crown capacitor using a tapered etch of a damascene lower electrode
US5994228A (en) * 1997-04-11 1999-11-30 Vanguard International Semiconductor Corporation Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes
US6027860A (en) 1997-08-13 2000-02-22 Micron Technology, Inc. Method for forming a structure using redeposition of etchable layer
TWI231293B (en) 1997-11-12 2005-04-21 Jsr Corp Transfer film
TW375777B (en) * 1998-04-08 1999-12-01 United Microelectronics Corp Etching process
US6541812B2 (en) 1998-06-19 2003-04-01 Micron Technology, Inc. Capacitor and method for forming the same
JP3287322B2 (ja) * 1998-12-28 2002-06-04 日本電気株式会社 半導体装置の製造方法
DE19919832A1 (de) * 1999-04-30 2000-11-09 Bosch Gmbh Robert Verfahren zum anisotropen Plasmaätzen von Halbleitern
KR100589490B1 (ko) * 2003-12-30 2006-06-14 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
JP2015002191A (ja) * 2013-06-13 2015-01-05 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
CN113659075B (zh) * 2020-05-12 2023-07-11 长鑫存储技术有限公司 电容打开孔的形成方法和存储器电容的形成方法
EP4002504A4 (fr) 2020-05-12 2023-03-01 Changxin Memory Technologies, Inc. Procédé de formation de trou d'ouverture de condensateur et procédé de formation de condensateur de mémoire

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4462882A (en) * 1983-01-03 1984-07-31 Massachusetts Institute Of Technology Selective etching of aluminum
JPS62128150A (ja) * 1985-11-29 1987-06-10 Nec Corp 半導体装置の製造方法
JPH01287956A (ja) * 1987-07-10 1989-11-20 Toshiba Corp 半導体記憶装置およびその製造方法
US4874723A (en) * 1987-07-16 1989-10-17 Texas Instruments Incorporated Selective etching of tungsten by remote and in situ plasma generation
US5183533A (en) * 1987-09-28 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method for etching chromium film formed on substrate
JPH01216577A (ja) * 1988-02-24 1989-08-30 Ricoh Co Ltd 半導体装置の製造方法
EP0416809A3 (en) * 1989-09-08 1991-08-07 American Telephone And Telegraph Company Reduced size etching method for integrated circuits
JPH03188628A (ja) * 1989-12-18 1991-08-16 Mitsubishi Electric Corp パターン形成方法
DE69133410T2 (de) * 1990-03-08 2005-09-08 Fujitsu Ltd., Kawasaki Schichtstruktur mit einem Kontaktloch für Flossenkondensatoren in Drams und Verfahren zur Herstellung derselben
JPH04142738A (ja) * 1990-10-04 1992-05-15 Sony Corp ドライエッチング方法
US5296095A (en) * 1990-10-30 1994-03-22 Matsushita Electric Industrial Co., Ltd. Method of dry etching
US5342481A (en) * 1991-02-15 1994-08-30 Sony Corporation Dry etching method
US5116460A (en) * 1991-04-12 1992-05-26 Motorola, Inc. Method for selectively etching a feature
JP3225559B2 (ja) * 1991-06-11 2001-11-05 ソニー株式会社 ドライエッチング方法
JP2913936B2 (ja) * 1991-10-08 1999-06-28 日本電気株式会社 半導体装置の製造方法
JP3215151B2 (ja) * 1992-03-04 2001-10-02 株式会社東芝 ドライエッチング方法

Also Published As

Publication number Publication date
KR960006822B1 (ko) 1996-05-23
FR2704689A1 (fr) 1994-11-04
DE4413152A1 (de) 1994-10-20
US5476807A (en) 1995-12-19
JPH06326061A (ja) 1994-11-25
DE4413152B4 (de) 2004-01-29

Similar Documents

Publication Publication Date Title
FR2704689B1 (fr) Procede de formation de motif fin dans un dispositif a semi-conducteur.
FR2671664B1 (fr) Procede de formation d'interconnexions multiniveaux dans un dispositif a semiconducteurs.
EP0666590A3 (fr) Méthode pour la fabrication de sillons dans un dispositif semi-conducteur.
FR2695594B1 (fr) Dispositif a semiconducteurs de forme plate et procede de fabrication.
FR2736474B1 (fr) Procede pour fabriquer un dispositif laser a semi-conducteur et dispositif laser a semi-conducteur
FR2780200B1 (fr) Dispositif et procede de formation d'un dispositif presentant une cavite a atmosphere controlee
FR2743016B1 (fr) Procede et dispositif pour travailler sur un materiau en forme de nappe
FR2676294B1 (fr) Procede de verrouillage pour carte a memoire.
EP1120822A4 (fr) Procede de production d'un dispositif a semi-conducteur
FR2697108B1 (fr) Procede de depot d'un semiconducteur composite formant un dispositif a semiconducteur.
FR2735714B1 (fr) Procede pour imprimer un graphisme sur une carte a memoire
EP1341224A4 (fr) Procede d'elaboration d'un dispositif semi-conducteur
FR2635413B1 (fr) Procede de fabrication pour un dispositif metal-oxyde-semiconducteur
FR2643193B1 (fr) Procede pour fabriquer des circuits integres a semi-conducteurs
EP0984485A4 (fr) Procede pour former le cablage dans un dispositif a semi-conducteur, et dispositif a semi-conducteur
EP0640933A3 (fr) Procédé et dispositif pour la reconnaissance des formes.
FR2779008B1 (fr) Procede de fabrication d'un dispositif a semiconducteur
FR2794538B1 (fr) Composition de revetement de dessus pour photoreserve et procede pour former un motif fin en l'utilisant
FR2782839B1 (fr) Procede de fabrication d'un dispositif a semiconducteur
FR2738670B1 (fr) Procede et appareil de formation d'un motif sur un substrat de circuit integre
FR2631487B1 (fr) Procede de fabrication pour un dispositif a semi-conducteur comprenant la formation de motifs en metal
EP1065714A4 (fr) Procede de fabrication d'un dispositif a semi-conducteurs
FR2680497B1 (fr) Procede et machine pour recouvrir un substrat.
FR2742592B1 (fr) Dispositif laser a semi-conducteurs et procede pour sa fabrication
FR2652681B1 (fr) Procede pour realiser un substrat de cablage combine.