HU185711B - Semiconductor storing element with two fets - Google Patents
Semiconductor storing element with two fets Download PDFInfo
- Publication number
- HU185711B HU185711B HU821577A HU157782A HU185711B HU 185711 B HU185711 B HU 185711B HU 821577 A HU821577 A HU 821577A HU 157782 A HU157782 A HU 157782A HU 185711 B HU185711 B HU 185711B
- Authority
- HU
- Hungary
- Prior art keywords
- semiconductor memory
- storage element
- transistor
- memory element
- semiconductor storage
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Heat Sensitive Colour Forming Recording (AREA)
Abstract
Die Erfindung betrifft ein Halbleiterspeicherelement mit zwei Feldeffekttransistoren, dessen Einsatz insbesondere auf dem Gebiet der integrierten Halbleiterspeicher fuer elektronische Rechner und Datenverarbeitungsanlagen erfolgt. Das Ziel der Erfindung ist es, ein Halbleiterspeicherelement zu schaffen, das bei einem niedrigen spezifischen Flaechenverbrauch und selbst bei weiterer Verkleinerung noch gut lesbar ist. Die Aufgabe der Erfindung besteht darin, ein Halbleiterspeicherelement mit 2 Feldeffekttransistoren zu schaffen, mit welchem die Lesespannung und damit die Lesegeschwindigkeit gegenueber bekannten Loesungen, bei gleichzeitig niedrigem spezifischem Flaechenverbrauch, erhoeht wird. Erfindungsgemaess wird die Aufgabe dadurch geloest, dass von den Gates des Transfer- und des Ladetransistors die Kapazitaeten C 2 und C 2 hoch x an die Wortleitung geschaltet sind. Die resultierende Schwellspannung des Ladetransistors liegt zwischen den resultierenden Schwellspannungen des Transfertransistors im "1"- bzw."0"-Zustand. Die erste Drain/Source-Elektrode des Transfertransistors ist direkt mit der Bitleitung verbunden.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DD81230022A DD160601A3 (de) | 1981-05-18 | 1981-05-18 | Halbleiterspeicherelement mit 2 feldeffekttransistoren |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| HU185711B true HU185711B (en) | 1985-03-28 |
Family
ID=5530961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| HU821577A HU185711B (en) | 1981-05-18 | 1982-05-18 | Semiconductor storing element with two fets |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5828866A (de) |
| CS (1) | CS240436B1 (de) |
| DD (1) | DD160601A3 (de) |
| DE (1) | DE3212945A1 (de) |
| HU (1) | HU185711B (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6025269A (ja) * | 1983-07-21 | 1985-02-08 | Hitachi Ltd | 半導体記憶素子 |
| JPH01133357A (ja) * | 1987-11-18 | 1989-05-25 | Fujitsu Ltd | 半導体記憶装置 |
| KR100229961B1 (ko) * | 1991-01-09 | 1999-11-15 | 피터 토마스 | 메모리셀 장치 및 동작방법 |
-
1981
- 1981-05-18 DD DD81230022A patent/DD160601A3/de not_active IP Right Cessation
-
1982
- 1982-04-07 DE DE19823212945 patent/DE3212945A1/de not_active Withdrawn
- 1982-05-03 CS CS823144A patent/CS240436B1/cs unknown
- 1982-05-18 HU HU821577A patent/HU185711B/hu unknown
- 1982-05-18 JP JP57082534A patent/JPS5828866A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CS240436B1 (en) | 1986-02-13 |
| DD160601A3 (de) | 1983-11-16 |
| DE3212945A1 (de) | 1982-12-09 |
| JPS5828866A (ja) | 1983-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5335205A (en) | DRAM using word line potential control circuitcircuit | |
| EP1158536A3 (de) | Halbleiterspeicheranordnung | |
| EP0090632B1 (de) | Statische Randomspeicheranordnung | |
| KR860002826A (ko) | 메모리 디바이스 | |
| KR950009234B1 (ko) | 반도체 메모리장치의 비트라인 분리클럭 발생장치 | |
| JPH10106272A (ja) | 半導体記憶装置 | |
| US5561626A (en) | Semiconductor memory with hierarchical bit lines | |
| EP0154547B1 (de) | Dynamischer Lese-Schreib-Direktzugriffsspeicher | |
| US4788457A (en) | CMOS row decoder circuit for use in row and column addressing | |
| US5796651A (en) | Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device | |
| US5999459A (en) | High-performance pass-gate isolation circuitry | |
| US4803662A (en) | EEPROM cell | |
| EP0073677A2 (de) | MIS Transistorschaltung mit einer Spannungshalteschaltung | |
| US6101140A (en) | Sense amplifier driver circuit for supplying a reduced driving voltage to sense amplifier | |
| HU185711B (en) | Semiconductor storing element with two fets | |
| EP0244628B1 (de) | Leseverstärker für eine Halbleiter-Speicheranordnung | |
| EP0262531B1 (de) | Halbleiterspeicheranordnung mit einer Datenbus-Rücksetzungsschaltung | |
| US4418401A (en) | Latent image ram cell | |
| US4779230A (en) | CMOS static ram cell provided with an additional bipolar drive transistor | |
| JPS61294695A (ja) | 半導体集積回路装置 | |
| US3936810A (en) | Sense line balancing circuit | |
| DE19611212C2 (de) | Halbleiter-Speichereinrichtung | |
| US5504711A (en) | Bit lines write circuit for SRAM memories | |
| US5224069A (en) | Ferroelectric capacitor memory circuit MOS setting and transmission transistors | |
| DE10314615B4 (de) | Verstärker mit verringertem Leistungsverbrauch |