IT1247303B - Dram avente circuiteria periferica in cui il contatto di interconnessione sorgente-pozzo di un transistor mos e' reso piccolo utilizzando uno strato di piazzuola e procedimento di fabbricazione di esso - Google Patents

Dram avente circuiteria periferica in cui il contatto di interconnessione sorgente-pozzo di un transistor mos e' reso piccolo utilizzando uno strato di piazzuola e procedimento di fabbricazione di esso

Info

Publication number
IT1247303B
IT1247303B ITMI911161A ITMI911161A IT1247303B IT 1247303 B IT1247303 B IT 1247303B IT MI911161 A ITMI911161 A IT MI911161A IT MI911161 A ITMI911161 A IT MI911161A IT 1247303 B IT1247303 B IT 1247303B
Authority
IT
Italy
Prior art keywords
source
dram
well
conductive layers
pitch
Prior art date
Application number
ITMI911161A
Other languages
English (en)
Inventor
Hideaki Arima
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI911161A0 publication Critical patent/ITMI911161A0/it
Publication of ITMI911161A1 publication Critical patent/ITMI911161A1/it
Application granted granted Critical
Publication of IT1247303B publication Critical patent/IT1247303B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

Transistor MOS (30a, 30b) incluso in un circuito periferico di una DRAM, il quale ha strati conduttori (16, 17) per l'interconnessione su superfici rispettive di una coppia di regioni sorgente-pozzo (33a, 33b). Gli strati (18) di interconnessione sorgente-pozzo sono collegati elettricamente alle regioni di sorgente-pozzo attraverso degli strati conduttori (16, 17). Uno della coppia di strati conduttori è formato nella medesima fase con una linea (15) di bit di una cella di memoria, mediante il medesimo materiale della linea di bit. L'altro della coppia di strati conduttori è formato nella medesima fase come un nodo di immagazzinamento (11) di un condensatore (10) della cella di memoria, impiegando il medesimo materiale del nodo di immagazzinamento. La coppia di strati conduttori impedisce connessione diretta tra lo strato di interconnessione sorgente-pozzo e le regioni di sorgente-pozzo, in modo tale che può essere realizzata riduzione nelle dimensioni delle regioni di sorgente-pozzo.
ITMI911161A 1990-05-01 1991-04-29 Dram avente circuiteria periferica in cui il contatto di interconnessione sorgente-pozzo di un transistor mos e' reso piccolo utilizzando uno strato di piazzuola e procedimento di fabbricazione di esso IT1247303B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2115642A JP2524862B2 (ja) 1990-05-01 1990-05-01 半導体記憶装置およびその製造方法

Publications (3)

Publication Number Publication Date
ITMI911161A0 ITMI911161A0 (it) 1991-04-29
ITMI911161A1 ITMI911161A1 (it) 1992-10-29
IT1247303B true IT1247303B (it) 1994-12-12

Family

ID=14667697

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI911161A IT1247303B (it) 1990-05-01 1991-04-29 Dram avente circuiteria periferica in cui il contatto di interconnessione sorgente-pozzo di un transistor mos e' reso piccolo utilizzando uno strato di piazzuola e procedimento di fabbricazione di esso

Country Status (5)

Country Link
US (4) US5486712A (it)
JP (1) JP2524862B2 (it)
KR (1) KR940005889B1 (it)
DE (1) DE4113932A1 (it)
IT (1) IT1247303B (it)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JP2535676B2 (ja) * 1991-04-01 1996-09-18 株式会社東芝 半導体装置の製造方法
JP3230696B2 (ja) * 1992-06-12 2001-11-19 ソニー株式会社 半導体記憶装置の製造方法
DE4221431A1 (de) * 1992-06-30 1994-01-05 Siemens Ag Herstellverfahren für einen Schlüsselkondensator
US5563089A (en) * 1994-07-20 1996-10-08 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
JPH07142597A (ja) * 1993-11-12 1995-06-02 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US5591680A (en) * 1993-12-06 1997-01-07 Micron Communications Formation methods of opaque or translucent films
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
JPH0870105A (ja) * 1994-08-30 1996-03-12 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US5904697A (en) * 1995-02-24 1999-05-18 Heartport, Inc. Devices and methods for performing a vascular anastomosis
JP2976842B2 (ja) * 1995-04-20 1999-11-10 日本電気株式会社 半導体記憶装置の製造方法
DE59506590D1 (de) * 1995-05-23 1999-09-16 Siemens Ag Halbleiteranordnung mit selbstjustierten Kontakten und Verfahren zu ihrer Herstellung
KR0155831B1 (ko) * 1995-06-20 1998-12-01 김광호 셀프얼라인을 이용한 듀얼패드셀 반도체장치 및 그것의 제조방법
JP3532325B2 (ja) 1995-07-21 2004-05-31 株式会社東芝 半導体記憶装置
JPH0992717A (ja) * 1995-09-21 1997-04-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR0168355B1 (ko) * 1995-11-02 1999-02-01 김광호 반도체장치의 배선 형성방법
JP2755243B2 (ja) * 1996-01-23 1998-05-20 日本電気株式会社 半導体記憶装置およびその製造方法
US5814887A (en) * 1996-01-26 1998-09-29 Nippon Steel Corporation Semiconductor device and production method thereof
US5783488A (en) * 1996-01-31 1998-07-21 Vlsi Technology, Inc. Optimized underlayer structures for maintaining chemical mechanical polishing removal rates
JP3242568B2 (ja) * 1996-04-12 2001-12-25 富士通株式会社 パターン形成方法
TW304281B (en) * 1996-05-14 1997-05-01 United Microelectronics Corp Manufacturing method of memory global planarization
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US7064376B2 (en) * 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US5712201A (en) * 1996-06-07 1998-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip
US5994730A (en) 1996-11-21 1999-11-30 Alliance Semiconductor Corporation DRAM cell having storage capacitor contact self-aligned to bit lines and word lines
JP3331910B2 (ja) * 1997-06-20 2002-10-07 日本電気株式会社 半導体装置及びその製造方法
KR100269317B1 (ko) * 1997-12-09 2000-12-01 윤종용 평탄화를위한반도체장치및그제조방법
JPH11121710A (ja) * 1997-10-09 1999-04-30 Fujitsu Ltd 半導体装置及びその製造方法
US6432793B1 (en) 1997-12-12 2002-08-13 Micron Technology, Inc. Oxidative conditioning method for metal oxide layer and applications thereof
US6110818A (en) * 1998-07-15 2000-08-29 Philips Electronics North America Corp. Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof
KR100276390B1 (ko) * 1998-08-10 2000-12-15 윤종용 반도체 메모리 장치 및 그의 제조 방법
US6015733A (en) * 1998-08-13 2000-01-18 Taiwan Semiconductor Manufacturing Company Process to form a crown capacitor structure for a dynamic random access memory cell
US6208004B1 (en) 1998-08-19 2001-03-27 Philips Semiconductor, Inc. Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof
US6596577B2 (en) * 1998-08-25 2003-07-22 Micron Technology, Inc. Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
US6174817B1 (en) 1998-08-26 2001-01-16 Texas Instruments Incorporated Two step oxide removal for memory cells
FR2785720B1 (fr) 1998-11-05 2003-01-03 St Microelectronics Sa Fabrication de memoire dram et de transistors mos
JP2000311992A (ja) 1999-04-26 2000-11-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
TW430983B (en) * 1999-10-15 2001-04-21 Taiwan Semiconductor Mfg DRAM with bend-type active region
US6200850B1 (en) * 1999-11-30 2001-03-13 United Microelectronics Corp. Method for forming a stacked capacitor
KR100352909B1 (ko) * 2000-03-17 2002-09-16 삼성전자 주식회사 반도체소자의 자기정렬 콘택 구조체 형성방법 및 그에의해 형성된 자기정렬 콘택 구조체
KR20020007848A (ko) * 2000-07-19 2002-01-29 박종섭 반도체 소자 및 그의 제조 방법
KR100363099B1 (ko) * 2001-01-12 2002-12-05 삼성전자 주식회사 주변회로부의 소오스/드레인 영역에 컨택패드를 갖는반도체 장치의 형성방법
JP3863391B2 (ja) 2001-06-13 2006-12-27 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2003234419A (ja) * 2002-02-08 2003-08-22 Mitsubishi Electric Corp 半導体装置の製造方法およびその方法により製造された半導体装置
KR100475084B1 (ko) * 2002-08-02 2005-03-10 삼성전자주식회사 Ｄｒａｍ 반도체 소자 및 그 제조방법
KR100513719B1 (ko) * 2002-08-12 2005-09-07 삼성전자주식회사 하프늄 산화막 형성용 전구체 및 상기 전구체를 이용한하프늄 산화막의 형성방법
US7297605B2 (en) * 2004-05-10 2007-11-20 Texas Instruments Incorporated Source/drain extension implant process for use with short time anneals
KR100960451B1 (ko) * 2008-02-29 2010-05-28 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1826120A (en) * 1928-06-25 1931-10-06 Burnett C Booth Lineman's platform
CH191184A (de) * 1937-05-03 1937-06-15 Binetti Severin Gerüstträger.
US2512174A (en) * 1949-04-08 1950-06-20 William O Roeder Sportsman's pocket-size collapsible tree seat
DE809611C (de) * 1949-04-08 1951-07-30 Heinz Schmidtke Zusammenlegbarer Hochsitz
JPH0618257B2 (ja) * 1984-04-28 1994-03-09 富士通株式会社 半導体記憶装置の製造方法
JPS61198780A (ja) * 1985-02-28 1986-09-03 Toshiba Corp 半導体装置の製造方法
US4614252A (en) * 1985-11-08 1986-09-30 Tarner David E Portable observation structure
US4641727A (en) * 1986-05-12 1987-02-10 A. B. Chance Company Electrically insulated temporary aerial platform
US4721213A (en) * 1987-03-13 1988-01-26 Eitel Jay M Equipment and method for installing apparatus at elevated locations
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
JPS63318151A (ja) * 1987-06-22 1988-12-27 Oki Electric Ind Co Ltd Ｄｒａｍメモリセル
JP2548957B2 (ja) * 1987-11-05 1996-10-30 富士通株式会社 半導体記憶装置の製造方法
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
JP2755591B2 (ja) * 1988-03-25 1998-05-20 株式会社東芝 半導体記憶装置
JPH0276257A (ja) * 1988-09-12 1990-03-15 Sharp Corp 半導体メモリ素子
JP2671466B2 (ja) * 1988-12-15 1997-10-29 富士通株式会社 半導体装置及びその製造方法
JPH0831534B2 (ja) * 1989-11-24 1996-03-27 シャープ株式会社 半導体記憶装置及びその製造方法
JP2519569B2 (ja) * 1990-04-27 1996-07-31 三菱電機株式会社 半導体記憶装置およびその製造方法
DE4113733C2 (de) * 1990-04-27 1996-01-25 Mitsubishi Electric Corp Feldeffekttransistor, Verfahren zur Herstellung derselben und DRAM unter Verwendung desselben
US5229314A (en) * 1990-05-01 1993-07-20 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation
US5236855A (en) * 1990-11-06 1993-08-17 Micron Technology, Inc. Stacked V-cell capacitor using a disposable outer digit line spacer
US5262343A (en) * 1991-04-12 1993-11-16 Micron Technology, Inc. DRAM stacked capacitor fabrication process
US5327994A (en) * 1993-08-05 1994-07-12 Smith Michael P Tree seat

Also Published As

Publication number Publication date
US5486712A (en) 1996-01-23
JP2524862B2 (ja) 1996-08-14
KR940005889B1 (ko) 1994-06-24
ITMI911161A1 (it) 1992-10-29
US5659191A (en) 1997-08-19
DE4113932A1 (de) 1991-11-14
US5949110A (en) 1999-09-07
ITMI911161A0 (it) 1991-04-29
JPH0412564A (ja) 1992-01-17
US5612241A (en) 1997-03-18
KR910020904A (ko) 1991-12-20

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Effective date: 19970429