JP2012147345A - Reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception system that is small in area, low in power consumption and low in cost.SOLUTION: After the frequency of a received signal is converted to an intermediate frequency on the basis of a reference signal, a channel is selected in an N-path filter for the intermediate frequency signal that is the frequency-converted signal. The reception system includes a frequency divider for generating an operating clock supplied to the N-path filter, and a multiphase clock generation section for generating multiphase clocks supplied to the N-path filter on the basis of the operating clock. The frequency divider receives the input of a signal having the same frequency as the reference signal input into the frequency converter, and generates the operating clock on the basis of the input signal. The frequency converter and the frequency divider receive the input of signals of the same frequency output from a single oscillator.

Description

  The present invention relates to a receiving system that converts a received signal into an intermediate frequency by a frequency converter and performs channel selection using a band limiting filter.

FIG. 5 shows a main configuration of a reception system in a conventional analog radio using a ceramic filter.
The conventional receiving system shown in FIG. 5 has a superheterodyne configuration. A received signal input to the receiving system is frequency-converted by the frequency converter 21 into a signal having an IF (Intermediate Frequency) frequency by a reference signal from the oscillator 25. An unnecessary signal is removed from the output signal of the frequency converter 21 by the band limiting filter 22, and only a signal having a desired frequency passes. As the band limiting filter 22, a ceramic filter of an external passive element is mainly used. The signal that has passed through the band limiting filter 22 is amplified by the IF amplifier 23 and output as a baseband signal by the detection circuit 24.

  Here, since a ceramic filter has conventionally been used as the band limiting filter 22, the IC (Integrated Circuit) configuration has been limited to the configuration surrounded by the broken line 26. For this reason, it is difficult to reduce the mounting area, and the ceramic filter has a high risk of peeling off after physical mounting, and measures such as further hardening with resin are indispensable as a precautionary measure. Man-hours are occurring.

On the other hand, an attempt has been made to make the whole IC by using another filter instead of the ceramic filter of the external passive element (for example, Patent Document 1).
FIG. 6 shows a main configuration of a reception system in a conventional analog radio using an N-pass filter. In the configuration shown in FIG. 6, the band limiting filter 37 is configured by an N-pass filter instead of the ceramic filter that is an external passive element.

From the received signal (RF (Radio Frequency) signal) that is input, unnecessary signals are removed by the RF filter 31 and a desired signal is extracted. The signal that has passed through the RF filter 31 is amplified by the RF amplifier 32 and then mixed with the signal from the oscillator 341 in the image rejection mixer 33 to be frequency-converted to the IF frequency.
The frequency-converted signal passes through the polyphase filter 35 and the anti-aliasing filter 36, and then an unnecessary signal is removed by the band limiting filter 37, and only a desired signal is output.

As the band limiting filter 37, an N-pass filter is used. The band limiting filter 37 operates with a signal obtained by dividing the signal from the oscillator 342 by the frequency divider 381 and an N-phase signal generated by the N-phase filter multiphase clock generation unit 382. Here, although the oscillators 341 and 342 are two signal sources that can generate signals of different frequencies, there are cases where two signal sources are included inside one oscillator.
The output of the band limiting filter 37 is input to a smoothing filter 39 to remove harmonics. The output of the smoothing filter 39 passes through an IF amplifier 40 and is then converted into a baseband signal by a detection circuit 41.

  The N-pass filter constituting the band limiting filter 37 can be configured using a switched capacitor filter (SCF). Generally, BPF (Band Pass Filter) is configured by frequency-converting LPF (Low Pass Filter), but the same BPF characteristic is better when BPF is configured using an N-pass filter than this. It can be realized with a low Q value. As a result, the capacitance ratio of the switched capacitor is reduced, and it becomes insensitive to the effects of device variations, operational amplifier gain, parasitic capacitance, etc., so that it is possible to realize a narrowband filter with high accuracy inside the IC. Become.

FIG. 7 shows an example of a basic configuration of an N-pass filter (when N = 4) using a switched capacitor filter (SCF).
In this example, SCFs 56 to 59 are connected in parallel via changeover switches 52 to 55 and 60 to 63, respectively. The input signal Vin from the anti-folding filter 36 is input via the changeover switch 51, and the output signal Vout is output to the smoothing filter 39 via the changeover switch 64.

  Here, the frequency of the input signal Vin and the frequency of the output signal Vout are set to f3. A clock signal is supplied from the frequency divider 381 to each changeover switch. The clock signal supplied to the changeover switches 51 and 64 is φ, and the clock signal supplied to the changeover switches 52 and 60 is φ1. The clock signal supplied to 53 and 61 is φ2, the clock signal supplied to the changeover switches 54 and 62 is φ3, and the clock signal supplied to the changeover switches 55 and 63 is φ4.

FIG. 8 is a diagram illustrating timings of the clock signals φ and φ1 to φ4. Here, the frequency of the clock φ is fs (= f4).
On the other hand, when the circuit of FIG. 7 functions as an N-pass filter, the frequencies of the clocks φ1 to φ4 need to be f3, which is the same frequency as the frequency of the input signal Vin and the frequency of the output signal Vout.

Here, the principle of the N-pass filter will be described below. Assuming that the transfer functions H (z) of the SCFs of the N paths are equal, the input voltage and the output voltage of the SCFs of the N paths are represented by VXin (z) and VXout (z) (X = 1, 2), respectively. ,..., N), the following equation holds:
H (z) = V1out (z) / V1in (z)
= V2out (z) / V2in (z)
= ...
= VNout (z) / VNin (z)

Therefore, the overall transfer function Htotal (z) is given by the following equation, where Vin (z) and Vout (z) are the input voltage and output voltage of the entire N-pass filter.
Htotal (z) = Vout (z) / Vin (z)
= {V1out (z) + V2out (z) + ... + VNout (z)} / {V1in (z) + V2in (z) + ... + VNin (z)}
= {H (z) · V1in (z) + H (z) · V2in (z) + ... + H (z) · VNin (z)} / {V1in (z) + V2in (z) + ... + VNin ( z)}
= H (z)
Here, the sampling rate of each path is expressed as 1 / NT = fs / N using the period T (= 1 / fs) of the clock φ shown in FIG. Further, the sampling rate fs / N of each path is the same as f3.

Next, it is assumed that the SCF is an LPF.
Since the sampling rate of each path is fs / N, as shown in FIG. 9, the frequency is “0” (f = 0) at each point where the frequency is fs / N, 2fs / N, 3fs / N,. ) And a replicated band pass filter (R-BPF) is formed at each point.

Here, considering the case where only one path is used, since the input frequency equal to or higher than the Nyquist frequency fs / (2N) of the path is turned back, the BPF at the frequency fs / N falls outside the Nyquist range and is used as the BPF. I can't understand.
On the other hand, considering the case where N paths are used, the Nyquist frequency of the entire N path is fs / 2, so the BPF at the frequency fs / N is in the Nyquist range and can be used as a BPF. It is.

Furthermore, since the R-BPF at frequencies 0, 2 · fs / N, 3 · fs / N,... Remains, another BPF (for example, a prefilter) is used as shown in FIG. Thus, by removing an undesired input frequency, a desired BPF characteristic can be obtained (Non-Patent Document 1).
In this way, an attempt is made to make the band limiting filter of the passive component into an IC, and in Patent Document 1, an N pass filter is used as the band limiting filter 37. As a result, the area and power consumption can be reduced compared to the switched capacitor filter of the same discrete filter.

Japanese Patent Laid-Open No. 2006-324795

Robik Gregorian and 1 other "ANALOG MOS INTEGRATED CIRCUITS FOR SIGNAL PROCESSING", John Wiley & Sons, Inc.

However, in the conventional receiving system, in order to supply the reference signal to the image rejection mixer 33 and the frequency divider 381, it is necessary to prepare the oscillators 341 and 342 as a plurality of signal sources, respectively. There are problems in terms of component cost and power consumption, such as the necessity of providing an oscillator and a PLL (phase locked loop) circuit.
FIG. 11 shows only the blocks that change the signal frequency among the blocks constituting the conventional receiving system. It should be noted that the block whose signal frequency does not change is omitted in FIG. Further, since the detection circuit 41 is a block for demodulating a signal, the notation is omitted in FIG.

The input received signal (frequency f1 ′) is mixed with the reference signal (frequency f2 ′) output from the oscillator 341 in the image rejection mixer 33 and converted to a band-pass IF signal (frequency f3 ′). .
The reference signal (frequency f6 ′) output from the oscillator 342, which is a signal source different from the oscillator 341, is converted into a frequency divider output signal (frequency f4 ′) by the frequency divider 381, and the band limiting filter 37 is obtained. To be supplied.

At the same time, the frequency divider output signal (frequency f 4 ′) is also supplied to the N-pass filter multiphase clock generation unit 382, and an N-phase clock is generated and supplied to the band limiting filter 37. At this time, the frequency of the N-phase clock must be the same as the frequency f3 ′ of the band-pass IF signal from the image rejection mixer 33.
The signal (frequency f3 ′) input to the band limiting filter 37 is band-limited and output. As a matter of course, the frequency of the signal output with the band limited is f3 ′.

Here, as described above, in order for the N-pass filter to function, the frequency of the band-pass IF signal from the image rejection mixer 33 and the clocks φ1 to φ4 from the N-pass filter multiphase clock generation unit 382 are used. The frequency needs to be the same frequency f3 ′.
Therefore, both the reference signal output from the oscillator 341 that is the source of the band-pass IF signal and the other reference signal output from the oscillator 342 that is the source of the clocks φ1 to φ4 have the same frequency. It is necessary to prepare an oscillator for generating such a reference signal. When the oscillator 341 and the oscillator 342 are provided in the IC, there are problems in terms of component cost and power consumption.

Further, when the oscillator 341 and the oscillator 342 do not exist inside the IC and each reference signal must be supplied from the outside, there is a possibility that desired reference signals cannot be secured. In particular, since the frequency f1 ′ of the input received signal is determined by the specifications of the receiving system, the degree of freedom in selecting each desired reference signal is not necessarily high.
In view of these problems, it is an object of the present invention to provide a receiving system that has a smaller area, lower power consumption, and lower cost than conventional ones.

  In order to solve the above problem, the present invention provides a frequency converter that converts a received signal to an intermediate frequency based on a reference signal, and a channel selection method for the intermediate frequency signal that is the frequency converted signal. A band limiting filter composed of an N-pass filter, a frequency divider for generating an operation clock supplied to the N-pass filter, and a multiphase clock supplied to the N-pass filter based on the operation clock A multiphase clock generation unit that receives the input of a signal having the same frequency as that of the reference signal input to the frequency converter. The receiving system is characterized in that the operation clock is generated on the basis thereof.

That is, when the band limiting filter is realized by an N-pass filter, a plurality of reference signals are not required, and the band limiting filter is realized by one reference signal.
As a result, it is possible to provide a receiving system that has a smaller area, lower power consumption, and lower cost than conventional receiving systems.
Further, the frequency converter and the frequency divider may be configured to accept input of a signal having the same frequency output from a single oscillator.
According to this configuration, it is possible to provide a receiving system that has a smaller area, lower power consumption, and lower cost than a conventional receiving system.
The reception signal, the reference signal, the intermediate frequency signal, and the operation clock may satisfy the conditions of (Expression 1), (Expression 2), and (Expression 3).

(In (Expression 1) to (Expression 3), f1 is the frequency of the received signal, f2 is the frequency of the reference signal, f3 is the frequency of the intermediate frequency signal, and f4 is the frequency of the operation clock)
According to this configuration, it is possible to provide a receiving system that has a smaller area, lower power consumption, and lower cost than a conventional receiving system.
In addition, the frequency converter, the band limiting filter, the frequency divider, and the multiphase clock generation unit are formed on the same IC (Integrated Circuit) chip, and the reference signal is external to the IC chip. It may be supplied from.
According to this configuration, it is possible to provide a receiving system with a smaller area, lower power consumption, and lower cost.

The band limiting filter may be provided in multiple stages.
According to this configuration, even when the band limiting filters are provided in multiple stages, it is possible to provide a reception system that has a smaller area, lower power consumption, and lower cost than the conventional reception system.
The receiving system may have a prefilter before the band limiting filter.
According to this configuration, the replica BPF can be suppressed.

According to the present invention, when the band limiting filter is realized by an N-pass filter, a plurality of reference signals are not required, and the band limiting filter is realized by one reference signal.
As a result, it is possible to provide a receiving system that has a smaller area, lower power consumption, and lower cost than conventional receiving systems.

It is a block diagram which shows the structural example of the receiving system which concerns on 1st Embodiment. It is the figure which extracted and showed only the block from which a signal frequency changes among the blocks which comprise the receiving system which concerns on 1st Embodiment. It is a block diagram which shows the structural example of the receiving system which concerns on 2nd Embodiment. It is a block diagram which shows the structural example of the receiving system which concerns on 3rd Embodiment. It is a block diagram which shows the structure of the conventional receiving system. It is a block diagram which shows the structure of the conventional receiving system. It is a figure which shows an example of a structure of the N pass filter used for the conventional receiving system. It is a figure which shows an example of the clock timing of the conventional N pass filter. It is a figure which shows the frequency characteristic of the conventional N pass filter. It is a figure which shows the frequency characteristic of the conventional N pass filter. It is the figure which extracted and showed only the block from which a signal frequency changes among the blocks which comprise the conventional receiving system.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In each drawing referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.
(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a receiving system according to the present embodiment.
The reception signal input to the reception system shown in FIG. 1 is band-limited by the RF filter 13 and then input to the frequency converter 1. Then, it is mixed with the reference signal by the frequency converter 1 and converted into an IF signal.

The converted IF signal passes through the variable gain amplifier and the antialiasing filter 2 and is input to the band limiting filter 3. The output of the band limiting filter 3 is such that an unnecessary signal is suppressed and only an IF signal of a desired channel is selected.
The band limiting filter 3 is composed of an N-pass filter and is a discrete system. In order to remove the clock signal for operating this and its harmonics, the signal output from the band limiting filter 3 passes through the smoothing filter 6. Then, the signal is amplified by an IF amplifier (limiting amplifier) 7 and finally converted into a baseband signal by a detection circuit 8.

Here, the reference signal input to the reception system is input to the frequency converter 1 and the same reference signal is also input to the frequency divider 4 at the same time. This is a feature of the reception system according to this embodiment. . And such a structure is implement | achieved by selecting the relationship of the frequency of each signal so that it may become a predetermined relationship so that it may mention later.
The signal frequency-divided by the frequency divider 4 is supplied to both the band limiting filter 3 and the N-path filter multiphase clock generator 5. Further, the multiphase clock generated by the N-path filter multiphase clock generator 5 is supplied to the band limiting filter 3. The band limiting filter 3 and the N-path filter multiphase clock generation unit 5 are the same as those in the conventional configuration shown in FIGS.

  Here, since each structure surrounded by the broken line 9 does not use a ceramic filter, it can be integrated. FIG. 2 shows only the blocks whose signal frequency changes among the blocks constituting the receiving system of FIG. In FIG. 2, the notation is omitted for blocks whose frequency does not change. Further, since the detection circuit 8 is a block for demodulating a signal, the notation is omitted in FIG.

The received signal (frequency f1) is mixed with the reference signal (frequency f2) in the frequency converter 1 and converted into a band-pass IF signal (frequency f3). The reference signal (frequency f 2) is converted into a frequency divider output signal (frequency f 4) by the frequency divider 4 and supplied to the band limiting filter 3.
At the same time, the frequency divider output signal (frequency f4) is also supplied to the N-pass filter multiphase clock generator 5. The N-phase filter multiphase clock generator 5 generates an N-phase clock, and the generated N-phase clock is supplied to the band limiting filter 3. The frequency of this N-phase clock is also the same as f3.

The signal (frequency f3) input to the band limiting filter 3 is output as a band limited signal. Of course, the frequency of this band-limited signal is f3.
At this time, the frequency f2 of the reference signal, the frequency f3 of the band-pass IF signal, and the frequency f4 of the frequency divider output signal are selected so that the following formulas 1, 2 and 3 are established.

  Specifically, for example, the frequency f3 is determined by Equation 1 from the relationship between the frequencies f1 and f2 of the input / output signals of the frequency converter 1. Further, the frequency f4 and the expression 3 determine the frequency f4 of the sampling clock of the band limiting filter 3 (N-pass filter). Furthermore, by setting the frequencies f2 and f3 so as to satisfy Expression 2, the receiving system of the present embodiment using only one reference signal can be realized.

As described above, the reference signal input to the frequency converter 1 and the reference input to the frequency divider 4 are selected by selecting the frequency of each signal so as to satisfy the predetermined relationship expressed by the above Equations 1 to 3. The signal becomes one and the reference signal can be shared. Therefore, it is not necessary to prepare separate oscillators for generating the reference signal.
In this embodiment, the reference signal is supplied from the outside of the IC. However, a single oscillator is provided inside the IC, and the reference signal is generated in this oscillator. Also good. In this case, since a plurality of oscillators are not prepared inside the IC, the component cost and power consumption can be reduced.

More specifically, for example, the specifications of the receiving system of the present embodiment include the frequency f1 of the received signal = 50.85 MHz, the frequency f2 of the reference signal = 50.4 MHz, the frequency f3 of the band-pass IF signal = 450 kHz, the minute The frequency f4 of the peripheral output signal can be selected to be 3.6 MHz.
In addition, as shown in FIG. 1, when the RF filter 13 is used before the frequency converter 1 and outside the IC (the portion surrounded by the broken line 9), it is unnecessary outside the desired passband. The signal is suppressed by the RF filter 13. Therefore, even when an N pass filter is used as the band limiting filter 3, it is possible to further reduce the chip area of the IC and reduce the power consumption.

(Second Embodiment)
FIG. 3 is a block diagram illustrating a configuration example of the receiving system according to the present embodiment.
The basic configuration is the same as the configuration shown in FIG. 1, but the band-limiting filter is divided into two stages, a band-limiting filter 3 ′ and a band-limiting filter 11, between which one more variable gain amplifier 10 is provided. Is put. Further, similarly to the first embodiment, in this embodiment, the frequency of each signal is set so as to satisfy the conditions of Expression 1, Expression 2, and Expression 3.
By combining variable gain amplifiers and band limiting filters in multiple stages in this way, a more suitable reception IF system can be constructed to amplify the desired signal frequency while suppressing unnecessary signals other than the desired signal frequency. It becomes.

In FIG. 3, the variable gain amplifier has two stages and the band limiting filter has two stages, but the number of stages is not limited to this. If the conditions of Expressions 1 to 3 are satisfied, the number of stages of the variable gain amplifier and the band limiting filter may be another number.
According to the receiving system according to the present embodiment, even when the band limiting filters are provided in multiple stages, the receiving system has a smaller area, lower power consumption, and lower cost than the conventional receiving system. Can be provided.

(Third embodiment)
FIG. 4 is a block diagram illustrating a configuration example of the receiving system according to the present embodiment.
When the RF filter 13 is used in the front stage of the frequency converter 1 as in the receiving system according to the first embodiment shown in FIG. 1, unnecessary signals outside the desired pass band are suppressed by the RF filter 13. Is done. However, in the present embodiment, the pre-filter 12 is provided before the N pass filter 3. Thereby, replica BPF (R-BPF) can be suppressed.

DESCRIPTION OF SYMBOLS 1 Frequency converter 2 Variable gain amplifier and anti-aliasing filter 3 Band-limiting filter (N pass filter)
4 Frequency Divider 5 N-phase Filter Multiphase Clock Generation Unit 6 Smoothing Filter 7 IF Amplifier 8 Detection Circuit 10 Variable Gain Amplifier 11 Band Limit Filter (N Pass Filter)
12 Pre-filter 13 RF filter 21 Frequency converter 22 Band limiting filter 23 IF amplifier 24 Detection circuit 25 Oscillator 31 RF filter 32 RF amplifier 33 Image rejection mixer 341 Oscillator 342 Oscillator 35 Polyphase filter 36 Antialiasing filter 37 Band limiting filter ( N pass filter)
381 Frequency divider 382 N-pass filter multilayer clock generator 39 Smoothing filter 40 IF amplifier 41 Detector circuits 51-55, 60-64 switches

Claims (6)

A frequency converter that converts the received signal to an intermediate frequency based on the reference signal;
A band limiting filter composed of an N-pass filter for selecting a channel for the intermediate frequency signal which is the frequency converted signal;
A frequency divider for generating an operation clock supplied to the N-pass filter;
A multi-phase clock generator for generating a multi-phase clock supplied to the N-pass filter based on the operation clock;
A receiving system comprising:
The frequency divider receives an input of a signal having the same frequency as the reference signal input to the frequency converter, and generates the operation clock based on the input signal.   The receiving system according to claim 1, wherein the frequency converter and the frequency divider receive an input of a signal having the same frequency output from a single oscillator. The received signal, the reference signal, the intermediate frequency signal, and the operation clock satisfy the conditions of (Equation 1), (Equation 2), and (Equation 3). Receiving system.

(In (Expression 1) to (Expression 3), f1 is the frequency of the received signal, f2 is the frequency of the reference signal, f3 is the frequency of the intermediate frequency signal, and f4 is the frequency of the operation clock) The frequency converter, the band limiting filter, the frequency divider, and the multiphase clock generator are formed on the same IC (Integrated Circuit) chip,
The receiving system according to claim 1, wherein the reference signal is supplied from the outside of the IC chip.   The receiving system according to any one of claims 1 to 4, wherein the band limiting filter is provided in multiple stages.   The receiving system according to claim 1, further comprising a pre-filter before the band-limiting filter.

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