JP3147062B2 - Sense amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a sense amplifier circuit, and more particularly to a sense amplifier circuit suitable for use in a read-only memory (ROM) integrated into a CMOS.

[0002]

2. Description of the Related Art A read-only storage device (hereinafter referred to as "ROM")
For example, Japanese Patent Application Laid-Open No. 6-28881 discloses a conventional sense amplifier circuit including a current source circuit connected in parallel to a data cell circuit to be read so as to suppress an increase in response time required for data reading. A sense amplifier circuit has been proposed. A conventional sense amplifier circuit will be described with reference to FIGS.

Referring to FIG. 4, a conventional sense amplifier circuit comprises a source follower circuit 1 comprising an N-channel transistor N1 and an inverter circuit IV1, a P-channel transistor P1 having a shorted gate and drain, and a gate. A current mirror circuit 2 comprising a P-channel transistor P2 connected to the gate and drain of the transistor P1; and an N-channel transistor N having a source grounded and a gate connected to a reference voltage source VR.
And a current source circuit 3 according to the second embodiment.

In the sense amplifier circuit proposed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 6-28881, a current source circuit 5 is connected in parallel with a data cell circuit 4 as shown in FIG.

Referring to FIG. 6, a source follower circuit 1
Is connected to the data cell circuit 4, the input and output of the inverter circuit IV1 are connected to the source and gate of the transistor N1, respectively, the input of the current mirror circuit 2 is connected to the drain of the transistor N1, and the current source circuit 3
Is connected to the output of the current mirror circuit 2 to become a data output point. The output point is connected to the inverter circuit IV2 as a buffer. The output of the current source circuit 5 is connected to the output of the source follower circuit 1 to the data cell circuit 4. And are connected in parallel.

Next, the operation of the conventional sense amplifier circuit will be described with reference to FIG. FIG. 5 shows a specific example of the data cell circuit 4 represented by a variable resistor in FIGS. 4 and 6.

In FIG. 5, 4 × 4 = 16 of M _{00 to} M ₃₃
The transistors are data cells, and the four transistors M _{S0 to} M _S3 are select circuits for selecting any one of the four data cell arrays of X = 0 to 3. Each data cell is constituted by a depletion type transistor for holding data, and an enhancement type transistor for holding no data.

The method of addressing individual data cells is as follows:
It is as follows.

The select circuit applies the "H" level only to the gate of the transistor on the selected line, and applies the "L" level otherwise.

The data cell section applies an "L" level only to the gate of the column to be selected, and applies an "H" level otherwise.

As a result, in the data cell array selected by the select circuit, only the cell of interest is given the "L" level to the gate, and the other cells connected in series are given the "H" level. In this case, the output resistance of the data cell including the select circuit is the depletion type of the selected data cell, that is, the series resistance of the on-resistance between the drain and source of each transistor of the selector only when data is held. . When data is not held, the output resistance becomes almost infinite.

For example, in FIG. 5, only two of M ₀₃ and M ₂₁ hold data. Turning now to the intended reading the data of M _21, address H, the address L of the selector unit and the data cell portion is set as shown in Table 1.

[0013]

[Table 1]

At this time, the output resistance of the data cell is as follows.

RO = R _ONS2 + R _ON20 + R _ON21 + R _ON22 +
R _ON23 However, the drain of R _ONS2 ... drain-source on-resistance of M _S2, the drain-source on-resistance of the R _ON20 ... M _20, the drain-source on-resistance of the _{R ON21 ... M 21, R ON22} ... M 22 -to-source on-resistance, drain-to-source on-resistance of the R _ON23 ... M _23.

[0016] In addition, when reading the data of M ₂₃ is,
The addresses H and L of the selector section and the data cell section are set as shown in Table 2.

[0017]

[Table 2]

[0018] At this time, the output resistance of the data _{cell, RO = R ONS2 + R ON20} + R ON21 + R ON22 + R CF23 however, is the resistance at the time of cut-off of R _CF23 ... M _23, is approximately RO → ∞.

Next, the operation of the sense amplifier unit will be described below.

The source follower circuit 1 is a circuit for outputting a certain potential at the output point of the data cell circuit 4, that is, at the source of the transistor N1. At the input of the source follower circuit 1, the source potential of the transistor N1, which is the output of the source follower circuit 1 itself, is inverted and amplified at a high gain by the inverter circuit IV1, and is negatively fed back to the gate.

Here, the source of the transistor N1 is
As loads, in addition to the equivalent resistance of the data cell circuit 4, the input capacitance of the inverter circuit IV1 and the transistor N1
And a stray capacitance C _{S1 including} a parasitic capacitance generated in a diffusion layer of each transistor of the data cell circuit 4.

Therefore, even when each data cell of the data cell circuit 4 has a low impedance as well as a high impedance, the output of the source follower circuit 1, that is, the output point of the data cell circuit 4, In a steady state, a voltage substantially close to input threshold voltage VT (IV1) of inverter circuit IV1 is generated.

Now, when the data cell selected by the data cell circuit 4 is one that holds data, a voltage of VT (IV1) is applied to the output resistance RO of the data cell, and i2 = VT (IV1) / RO Flows out from the drain of the transistor P1, which is the input of the current mirror circuit 2.

The signal current i2 changes depending on how many data cells in the selected data cell array hold data in other data cells connected in series to the data cell of interest. That is, when all the other data cells are of the depletion type, the maximum value is i2 _MAX , and when all of the other data cells are of the enhancement type, the minimum value is i2 _MIN . In addition, when the selected data cell does not hold data, no current flows from the drain of the transistor P1.

Here, if the output current of the current mirror circuit 2 when the operating point of the transistor P2 is in the saturation region is 1: 1 with respect to the input, similarly, when the operating point is in the saturation region. The transistor N2 of the current source circuit 3 applies a bias to the gate terminal of the transistor N2 such that a current of, for example, i _DS = i2 _MIN / 2 flows. As a result, when the data cell selected by the data cell circuit 4 is for holding data, and the signal current i2 flows, the output potential of this sense amplifier circuit becomes "H". Is "L". That is, data stored as the difference between the threshold values of the MOS transistors of the depletion type and the enhancement type can be converted into a potential difference and output.

FIG. 7 is a diagram showing voltage and current waveforms showing an example of the operation of the source follower circuit 1. In the drawing, a broken line indicates that a non-data holding cell is selected from a data holding data cell in a general sense amplifier circuit without the current source circuit 5 among conventional sense amplifier circuits. The voltage and current waveforms of each part of the sense amplifier circuit when the data holding cell is selected again,
VG1 is the gate voltage of the transistor N1 of the source follower circuit 1, VS1 is the source voltage, i1 is the current flowing from the source, and i3 is the current flowing into the current source circuit 5 of FIG.

In a general sense amplifier circuit having no current source circuit 5, when a data cell changes to high impedance with a change in an address signal, a current flowing from the transistor N1 of the source follower circuit 1 causes
The stray capacitance C _S1 (see FIG. 5) is charged and the transistor N
The source potential V _S1 of ₁ rises. Then inverter IV
1 discharges the parasitic capacitance connected to the gate terminal of the transistor N1 to the ground potential, and the gate potential V
_G1 becomes the ground potential, and the transistor N1 is cut off.
As a result, the signal current i1 becomes 0.

On the other hand, when the data cell circuit changes to low impedance, since the transistor N1 of the source follower circuit 1 is still cut off, the floating capacitance C _S1 is discharged by the equivalent resistance RO of the data cell, and the source of the transistor N1 is discharged. The potential V _S1 falls with a time constant τ = C _S1 × RO. Then, the parasitic capacitance connected to the gate terminal of the transistor N1 is charged by the negative feedback of the inverter IV1, the gate potential _VG1 starts to increase, and the transistor N1 is turned on after a time Δt. As a result, the charging of the floating capacitance C _S1 and the supply of current to the data cell are started, and the source potential V _S1 of the transistor N1 also starts to increase.
As V _S1 increases, the signal current i1 also increases. Rise of the gate potential V _G1 of the transistor N1, the source potential V _S1
Stops when it reaches VT (IV1).

In such a general sense amplifier circuit, in the rising process of the signal current i1, the signal current i1 does not flow at all during the period Δt after the address change. While the source-to-source bias is shallow, the drain-source resistance is large and the rise of the signal current i1 is slow.

In this way, by the time the signal current i3 crosses the threshold, the address change causes Δt + α = t _d2
Delay occurs.

On the contrary, since the falling of the signal current i1 can be performed together with the address switching, the delay is small.

That is, the rising process of the signal current i1 is a bottleneck, and the response time required for data reading is long.

In order to solve such a problem, the same inventor as the present application disclosed in Japanese Patent Application Laid-Open No. Hei 6-28881 that the current source circuit 5 was connected in parallel with the data cell circuit 4 as shown in FIG. The proposed configuration was proposed. In FIG. 7, what is indicated by a solid line is a sense amplifier circuit having the current source circuit 5 shown in FIG. 7 shows voltage and current waveforms of each part of the sense amplifier circuit when a holding cell is selected.

Referring to the voltage / current waveform diagram of FIG. 7, the difference from the operation of the general sense amplifier circuit shown in FIG. 4 is that the data cell becomes high impedance and the current i2 flowing through the data cell circuit becomes zero. Even if the current source circuit 5
As a result, a current i3 flows through the source follower circuit 1,
This means that the source follower circuit 1 does not cut off during the entire operation period.

The dead time of the source follower circuit 1 when the signal current i1 rises is eliminated, and the output impedance of the source follower circuit 1 is small from the beginning. There delay t _d1 up across the threshold is suppressed only dominant to delay the charging time of the gate capacitance of the source follower circuit 1.

[0036]

However, the conventional sense amplifier circuit shown in FIG. 6 has a problem that power consumption increases.

The reason is that the current source circuit connected in parallel with the data cell circuit is configured such that the current always flows through the source follower circuit in order to suppress the time lag at the rise of the signal current. It is.

Accordingly, the present invention has been made in view of the above problems, and has as its object to selectively control a current supplied to a source follower circuit from a current source circuit connected in parallel with a data cell circuit. Another object of the present invention is to provide a sense amplifier circuit that realizes low power consumption without reducing performance by reducing only unnecessary current.

[0039]

In order to achieve the above object, a sense amplifier circuit according to the present invention connects a data cell circuit of a memory to be read to a source and an input of a current mirror circuit as a load to a drain. And a current follower circuit connected in parallel to the data cell circuit and controlled by read data.

[0040]

Embodiments of the present invention will be described. In a preferred embodiment of the sense amplifier circuit of the present invention, a data cell circuit to be read (FIG. 1)
4), a current source circuit (5a in FIG. 1) in which the output current is controlled by the read data, and turning on / off the output current of the current source circuit (5a in FIG. 1) with the read data as an input. Control circuit for control (6 in FIG. 1)
And. According to the embodiment of the present invention, similarly to the conventional sense amplifier circuit shown in FIG. 6, in addition to the effect that the response time in data reading can be prevented from increasing, the increase in the current consumption can be further exemplified. As about 50
%.

[0041]

Next, in order to describe the above-mentioned embodiment of the present invention in more detail, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the sense amplifier circuit of the present invention. In FIG. 1, the same or equivalent elements as those shown in FIG. 6 are denoted by the same reference numerals.

Referring to FIG. 1, in one embodiment of the present invention, the sense amplifier circuit includes a source follower circuit 1 including an N-channel transistor N1 and an inverter circuit IV1, a P-channel transistor P1 and a transistor P2. Current mirror circuit 2 and a current source circuit 3 including an Nch transistor N2 whose source is grounded.
, A control circuit 6, and a current source circuit 5 a whose output current is controlled by the control circuit 6.

A data output point which is a connection point between the output of the current mirror circuit 2 and the current source circuit 3 is provided as an output buffer
Inverter circuit IV2 is connected.

In one embodiment of the present invention, the control circuit 6 which receives the output of the inverter circuit IV2 as input controls the output current i3 of the current source circuit 5a according to the read data, and the output of the current source circuit 5a is , Is connected in parallel with the data cell circuit 4 to the output of the source follower circuit 1.

FIG. 2 is a diagram for explaining the operation of one embodiment of the present invention. In the state where a data holding data cell is selected, a data non-holding cell is selected, and the data holding cell is changed again. FIG. 5 is a diagram showing voltage and current waveforms of each part of the sense amplifier circuit when selected. V _G1 is the gate voltage of the transistor N1 of the source follower circuit 1, V _S1 is the source voltage, i1 is the current flowing from the source, and i3 is the current flowing in the current source circuit 5 of FIG. The operation of one embodiment of the present invention will be described below with reference to FIG.

The difference between the operation of the embodiment of the present invention and the conventional sense amplifier circuit shown in FIG. 6 is that in the embodiment of the present invention, the data cell circuit 4 has a high impedance and the current i2 = 0. Current source circuit 5a only when
This causes a current i3 to flow through the source follower circuit 1.

As a result, in one embodiment of the present invention, even when the transistor N1 temporarily cuts off at the time of the fall of the signal current i1, the source follower circuit 1 starts to operate at the time of the rise of the signal current i1. The dead state can be eliminated first.

In other words, in the embodiment of the present invention, if it is assumed that data "0" and "1" are statistically read by 50% each, a problem occurs in the conventional sense amplifier circuit shown in FIG. 6 can be reduced to 50%, and the operation effect obtained by the conventional sense amplifier circuit shown in FIG. 6 is almost the same as the delay t until the signal current i1 rises and crosses the threshold. _d1 is suppressed to only a delay that makes the charging time of the gate parasitic capacitance of the source follower circuit 1 dominant.

The other operations are the same as those of the conventional sense amplifier circuit described with reference to FIGS. 6 and 7, and therefore the description thereof is omitted.

The present invention is not limited to the configuration of the above embodiment, and various modifications can be made within a range according to the principle of the present invention.

FIG. 3 shows an N-channel transistor N as the control circuit 6 in the embodiment of the present invention shown in FIG.
And a control circuit 6 comprising a transfer gate circuit comprising a P-channel transistor P3 and a P-channel transistor P3 and an inverter IV3. Source follower circuit 1 via gate circuit
Is connected in parallel with the data cell circuit 4, and the output of the inverter IV3, which receives the output OUT of the inverter IV2 constituting the output buffer, is connected to the gate of the P-channel transistor P3, and the output of the inverter IV2 is It is configured to be connected to the gate of the N-channel transistor N3.

As described above, when the data cell circuit enters the high impedance state, the stray capacitance C _S1 (see FIG. 5) is charged by the inflow current from the transistor N1 of the source follower circuit 1, and the source potential V of the transistor N1 is charged.
_S1 is cut off the gate potential V _G1 transistor N1 becomes the ground potential of the transistor N1 by the negative feedback of elevated inverters IV1, thereby, a signal current i1 is zero. At this time, the data output point (the connection point between the output of the current mirror circuit 2 and the current source circuit 3) transits to a low level, the output OUT of the inverter IV2 goes to a high level,
The transistors N3 and P3 of the transfer gate are both turned on, and the output of the transistor N4, which is the current source circuit 5a, is connected to the source of the transistor N1 of the source follower circuit 1 and the current (sink current) i3 is supplied to the source follower circuit 1.
Flows, the source potential drops, the gate potential of the transistor N1 rises via the inverter IV1, and the transistor N1 becomes conductive.

[0054]

As described above, according to the sense amplifier circuit of the present invention, similarly to the sense amplifier circuit described in Japanese Patent Application Laid-Open No. 6-28881, an increase in response time in data reading can be prevented. , And an increase in current consumption can be reduced by about 50%.

The reason is that the present invention has a current source circuit connected in parallel to the data cell circuit to be read and controlled by the read data.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of a sense amplifier circuit of the present invention.

FIG. 2 is a waveform diagram for explaining an operation of the sense amplifier circuit according to one embodiment of the present invention;

FIG. 3 is a diagram showing an example of a specific circuit configuration in an embodiment of the sense amplifier circuit of the present invention.

FIG. 4 is a diagram showing an example of a circuit configuration of a conventional general sense amplifier circuit.

FIG. 5 is a diagram showing an example of a circuit configuration including a data cell circuit for explaining the operation of a conventional sense amplifier circuit.

FIG. 6 shows another conventional sense amplifier circuit,
FIG. 2 is a diagram showing an example of a circuit configuration of a sense amplifier circuit proposed in Japanese Patent No. 288881;

FIG. 7 is a waveform chart showing an example of the operation of the conventional sense amplifier circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source follower circuit 2 Current mirror circuit 3,5,5a Current source circuit 4 Data cell circuit 6 Control circuit N1, N2, N3, N4 N-channel transistor P1, P2, P3 P-channel transistor

Claims (4)

(57) [Claims] 1. A source follower circuit having a transistor of a first conductivity type, wherein a data cell circuit of a memory to be read is connected to a source and an input terminal of a current mirror circuit as a load is connected to a drain, and the data cell circuit. And a current source circuit connected in parallel to the sense amplifier circuit, comprising: means for controlling an output current of the current source circuit by read data. 2. The sense amplifier circuit according to claim 1, wherein said current source circuit is controlled to output a current only when a signal current does not flow through said data cell circuit. 3. A source follower circuit having a transistor of a first conductivity type, wherein a data cell circuit of a memory to be read is connected to a source and an input terminal of a current mirror circuit as a load is connected to a drain; A current source circuit connected in parallel with the data cell circuit to the source of the transistor of the type, and circuit means for controlling on / off of the output current of the current source circuit by read data, wherein the current source circuit is A sense amplifier circuit controlled to output a current only when a signal current does not flow through the data cell circuit. 4. A source follower circuit having a transistor of the first conductivity type having a data cell circuit of a memory to be read connected to a source and an input terminal of a current mirror circuit as a load connected to a drain, and a current source circuit. Based on the potential of a data output point that is an output terminal node of the current mirror circuit, the current source circuit is connected or disconnected to the source of the first conductivity type transistor in parallel with the data cell circuit to be read. a switching circuit for the no signal current flows through the data cell circuit when the source follower circuit is cut off, so that current flows from the current supply circuit to the switch circuit is turned on the first conductivity type transistor A sense amplifier circuit characterized in that: