JP4903014B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4903014B2 JP4903014B2 JP2006139622A JP2006139622A JP4903014B2 JP 4903014 B2 JP4903014 B2 JP 4903014B2 JP 2006139622 A JP2006139622 A JP 2006139622A JP 2006139622 A JP2006139622 A JP 2006139622A JP 4903014 B2 JP4903014 B2 JP 4903014B2
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- Prior art keywords
- resin layer
- groove
- semiconductor device
- semiconductor chip
- mounting surface
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/856—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/944—Dispositions of multiple bond pads
- H10W72/9445—Top-view layouts, e.g. mirror arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
(1)樹脂層には半田端子がそれぞれ接続される金属製のポストを複数設け、溝は樹脂層の外側縁に沿って外側縁とポストとの間に設けたこと。
(2)半導体チップ及び樹脂層は平面視矩形形状とし、溝は矩形形状の樹脂層の4つの外周縁のうち、隣り合った2つの外周縁に沿って設けたこと。
(3)溝は装着面に対して所定の角度に傾斜させたこと。
(4)溝は幅方向に沿って深さの異ならせた段差を有すること。
10 半導体チップ
11 電極
12 電極配設面
20 樹脂層
21 ポスト
22 再配線
23 溝
24 外側縁
30 半田端子
Claims (5)
- 一側面に複数の電極を設けた半導体チップと、前記電極が形成されている前記半導体チップの電極配設面に重ね合わせて設けた樹脂層を備え、この樹脂層の表面を装着面としてアンダーフィル材を介して実装基板に装着される半導体装置において、
前記樹脂層の装着面の外側縁に沿ってのみ溝を設け、当該溝により前記装着面を複数の面に分断したことを特徴とする半導体装置。 - 前記樹脂層には、半田端子がそれぞれ接続される金属製のポストを複数設け、
前記溝は、前記樹脂層の外側縁に沿って、外側縁と前記ポストとの間に設けたことを特徴とする請求項1記載の半導体装置。 - 前記半導体チップ及び前記樹脂層は平面視矩形形状とし、前記溝は、矩形形状の前記樹脂層の4つの外周縁のうち、隣り合った2つの外周縁に沿って設けたことを特徴とする請求項2記載の半導体装置。
- 前記溝は、前記装着面に対して所定の角度に傾斜させたことを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。
- 前記溝は、幅方向に沿って深さの異ならせた段差を有することを特徴とする請求項1〜
3のいずれか1項に記載の半導体装置。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006139622A JP4903014B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体装置 |
| US11/798,938 US20070267757A1 (en) | 2006-05-18 | 2007-05-17 | Semiconductor device |
| US12/457,816 US20090261467A1 (en) | 2006-05-18 | 2009-06-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006139622A JP4903014B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007311575A JP2007311575A (ja) | 2007-11-29 |
| JP4903014B2 true JP4903014B2 (ja) | 2012-03-21 |
Family
ID=38711280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006139622A Active JP4903014B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US20070267757A1 (ja) |
| JP (1) | JP4903014B2 (ja) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007044620A1 (de) * | 2007-09-19 | 2009-04-16 | Semikron Elektronik Gmbh & Co. Kg | Anordnung mit einer Verbindungseinrichtung und mindestens einem Halbleiterbauelement |
| JP2010171107A (ja) * | 2009-01-21 | 2010-08-05 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
| IT201700103511A1 (it) * | 2017-09-15 | 2019-03-15 | St Microelectronics Srl | Dispositivo microelettronico dotato di connessioni protette e relativo processo di fabbricazione |
| JP7613020B2 (ja) * | 2020-07-28 | 2025-01-15 | 株式会社ソシオネクスト | 半導体装置の製造方法、半導体パッケージ及び半導体パッケージの製造方法 |
| EP4210096A4 (en) * | 2020-09-25 | 2023-11-08 | Huawei Technologies Co., Ltd. | Chip and manufacturing method therefor, and electronic equipment |
| US12035475B2 (en) * | 2021-05-07 | 2024-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with stress reduction design and method for forming the same |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100205321B1 (ko) * | 1996-12-30 | 1999-07-01 | 구본준 | 크랙방지 패턴을 갖는 반도체소자의 제조방법 |
| US6011301A (en) * | 1998-06-09 | 2000-01-04 | Stmicroelectronics, Inc. | Stress reduction for flip chip package |
| JP3446825B2 (ja) * | 1999-04-06 | 2003-09-16 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
| US6710446B2 (en) * | 1999-12-30 | 2004-03-23 | Renesas Technology Corporation | Semiconductor device comprising stress relaxation layers and method for manufacturing the same |
| JP3866073B2 (ja) * | 2001-10-10 | 2007-01-10 | 株式会社フジクラ | 半導体パッケージ |
| JP2003347471A (ja) * | 2002-05-24 | 2003-12-05 | Fujikura Ltd | 半導体装置及びその製造方法 |
| US7064452B2 (en) * | 2003-11-04 | 2006-06-20 | Tai-Saw Technology Co., Ltd. | Package structure with a retarding structure and method of making same |
| US7084011B2 (en) * | 2003-12-30 | 2006-08-01 | Texas Instruments Incorporated | Forming a chip package having a no-flow underfill |
| CN100411155C (zh) * | 2004-01-27 | 2008-08-13 | 株式会社村田制作所 | 层叠型电子元器件及其制造方法 |
| US7830011B2 (en) * | 2004-03-15 | 2010-11-09 | Yamaha Corporation | Semiconductor element and wafer level chip size package therefor |
| JP2006100534A (ja) * | 2004-09-29 | 2006-04-13 | Casio Micronics Co Ltd | 半導体装置 |
| DE102005003390B4 (de) * | 2005-01-24 | 2007-09-13 | Qimonda Ag | Substrat für ein FBGA-Halbleiterbauelement |
| JP4738971B2 (ja) * | 2005-10-14 | 2011-08-03 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
-
2006
- 2006-05-18 JP JP2006139622A patent/JP4903014B2/ja active Active
-
2007
- 2007-05-17 US US11/798,938 patent/US20070267757A1/en not_active Abandoned
-
2009
- 2009-06-23 US US12/457,816 patent/US20090261467A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US20090261467A1 (en) | 2009-10-22 |
| JP2007311575A (ja) | 2007-11-29 |
| US20070267757A1 (en) | 2007-11-22 |
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