JPH011033A - computer equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application If) The present invention relates to a computer device, and in particular, to a computer device having a high-speed saving and recovery function of a register file during a subroutine number call, return, etc. The present invention relates to computer equipment.

(Prior art) Conventionally, saving and restoring register files associated with subroutine calls, returns, etc. has been performed using, for example, PUSH and POP.
It was ij due to a program such as an instruction. However, this method has the problem of subroutine calls and overhead during lean, which hinders speeding up of processing.

Therefore, a method using register windows has been proposed to solve this problem (Reduced I n5
truct! on Set GoIIlputer A
rel+Itecturcs ror VLSI.

M, G, Il, Katcvcnis, HIT Pre.
ss) o However, with this method, although the contents of the register are saved as the register window changes when the subroutine is called, there is a problem in that the register information of the calling routine before the subroutine call changes. Ta.

In addition to this, a method of using a -register window and a normal register file in combination may be considered, but it is not possible to solve the drawbacks of both.

Such a problem becomes a significant problem especially when a program using Prolog is executed. That is, in Prolog, it is necessary to save register file information every time there is a choice point.
Register information must remain even after register file information is saved. Moreover, when a backtrack occurs, it is necessary to restore the register file to the state of the previous choice point. PrOIOg
In non-deterministic inference processing in , such choice points and backtracking are frequently repeated. Therefore, there is a problem in that the time loss during saving and restoring the register file leads to a significant reduction in processing time.

(Problems to be Solved by the Invention) As described above, in the program-based method of the prior art, registers and registers are used for subroutine calls, returns, Prolog choice points, and backtracking.
File save and restore operations cannot be performed at high speed, and the method using a register window has the problem that the register information of the caller disappears.

SUMMARY OF THE INVENTION An object of the present invention is to solve such conventional problems and provide a computer device in which caller information does not disappear and overhead is reduced when saving, restoring, and restoring a register file.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a computer system in which instructions sequentially fetched into a prefetch buffer are executed by an instruction execution unit in a pipeline operation. It is equipped with a resource management means that detects a cycle in which no execution is performed in the instruction execution unit, that is, an empty cycle of execution resources, and instructs saving and restoring the contents of the register file based on the information etc. The present invention is characterized by comprising a save/recovery instruction inserting means for inserting a register file save/recovery instruction into a vacant cycle of the execution resource based on a save/recovery instruction from the means.

(Operation) When an instruction fetch is made to wait due to a cache miss, for example, or when a break occurs in the pipeline due to execution of a jump instruction, execution in the instruction execution means is stopped, and an idle cycle of execution resources occurs. When the resource management means detects such an empty cycle of the execution resource, it sends an evacuation/recovery command to the evacuation/recovery command insertion means. The save/recovery instruction insertion means generates a register/file save/recovery instruction and inserts it into the empty cycle. Therefore, the instruction execution means saves and restores the register file in the vacant cycle.

As described above, according to the present invention, when it is necessary to save and restore a register file, the register file is saved and restored in this cycle, denying that a cycle in which execution resources are free will always occur. Since the save/recovery instructions for the register file are inserted, machine cycles can be used efficiently and save/recovery of the register file can be prevented from becoming an overhead during subroutine calls, returns, etc.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, a part of the instruction code stored in the main memory 2 is copied into the instruction cache section 1.

The instruction code stored in the instruction cache unit 1 is fetched into the brief fetch buffer 73 every machine cycle.
The instruction decoder 4 interprets the instruction and stores it in the pipeline register 5 at the next stage. The instructions stored in the pipeline register 5 are executed by the instruction execution unit 6, and the results are stored in the register file unit 7. The data cache unit 8 temporarily stores data between the main memory 2 and the register file unit 7.

When the resource management unit 9 confirms that an empty cycle of execution resources occurs from the instruction code fetched into the prefetch buffer 3, the resource management unit 9 sends an evacuation/recovery instruction insertion unit 10
Outputs register file save/restore commands. When the above-mentioned command is input manually, the save/recovery instruction insertion unit 10 inserts a register file save/recovery instruction into an empty machine cycle in the instruction decoder 4.

In the above configuration, when a subroutine call, choice, point, subroutine return, or back track occurs, the contents of the register file section 7 must be saved to the data cache section 8 or restored. The saving and restoring operations of the register file section 7 will be explained below with reference to FIG.

The figure shows six phases of a machine cycle including a jump instruction. M1 to M6 indicate machine cycles. F is a phase in which the instruction code is fetched into the prefetch buffer 3, D is a phase in which the fetched instruction code is decoded in the instruction decoder 4, and E is a phase in which the instruction is executed in the instruction execution unit 6, and these are executed by pipeline operation. executed.

If the instruction code in the fetch phase F2 of the machine cycle M2 is a jump instruction, the machine cycle M3 is not a decode phase but a jump phase J in which the program counter is rewritten. After that, a new fetch phase F is started from machine cycle M4.
3, followed by a decoding phase D3 and an execution phase E3.

Therefore, machine cycle M4. In M5, there is no execution phase in which an instruction is executed, that is, a jump instruction has occurred, which means that an empty cycle has occurred in the instruction execution unit 6. In the present invention, this empty cycle is utilized to save and restore registers between the register file unit 7 and data cache unit 8 in FIG.

SRD in FIG. 2 is a decoding phase for saving and restoring registers, and SRE is an execution phase for saving and restoring registers. When a jump instruction occurs in the fetch phase F2 of the machine cycle M2, the resource management section 9 detects this and outputs an evacuation/recovery instruction to the evacuation/recovery instruction insertion section 10. When the save/recovery command insertion unit 10 receives the above command, it generates an instruction code for save/recovery, and inserts this into the instruction decoder 4. The inserted instruction code is decoded in the save/restore decode phase 5RDI of machine cycle M3 in FIG. 2, and executed in the save conflict recovery execution phase 5REI of machine cycle M4. Similar operations are performed in the decoding phase 5RD2 of the machine cycle M4 and the execution phase 5RE2 of the machine cycle M5.

The above is an example of a jump instruction, but register file saving and restoring operations are also required when a cache miss occurs. The operation in this case is also substantially the same. For example, when the instruction code to be executed is not stored in the instruction cache section 1 of FIG. 1, a signal indicating a cache miss is output from the instruction cache section 1 to the resource management section 9.

When a cache miss occurs, it is necessary to newly store the necessary instruction code from the main memory 2 into the instruction cache unit 1. During this period, the instruction execution section 6 becomes an empty machine cycle, so the resource management section 9 can cause the instruction execution section 6 to save and restore the register file via the save and recovery instruction insertion section 10.

The above operation is shown in FIG. When a cache miss occurs in the instruction fetch phase of machine cycle M2, the instruction execution unit 6 executes the machine cycles M 4 , M 5 ,
The periods M 6 and M 7 can be used as execution periods for saving and restoring registers.

Instruction decoder 4 for register file saving/111 restoration
As the output, for example, a flagged N OP (No PeraLion) instruction as shown in FIG. 4 can be used. In this example, a flag of 0 is a save instruction, and a flag of 1 is a recovery instruction.

According to the present embodiment described above, the register file is saved and restored using the idle time of the machine cycle, so that the above-mentioned register saving and recovery is performed at the time of subroutine call, return, choice point, or back track. There is no additional overhead, and the calling routine's information is reliably preserved.

In addition, this invention -L, ic! In fact, it is not limited to the Arashi example, and various variations can be made without departing from the gist of the case.
3 is possible.

For example, in the above embodiment, an empty cycle of execution resources is detected based on the instruction code fetched into the prefetch buffer 3, but as shown in FIG. It is also possible to detect idle cycles of resources.

Further, in the actual example shown in FIG. 1, the save/restore instruction is inserted into the instruction decoder 4, or alternatively, as shown in FIG. 5, the save/restore instruction may be inserted into the vibe line register 5.

Furthermore, it is possible to apply the present invention to a method in which decoded instruction codes are prepared and supplied to the prefetch buffer 3.

[Effects of the Invention] As described above, according to the present invention, register files are saved and restored using free cycles of execution resources, so register file saving and recovery operations are performed using subroutine calls and subroutine calls. There is no overhead for returns, Prolog choice points, back tracks, etc. Therefore, it is possible to speed up the processing while reliably retaining the caller information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a computer device according to an embodiment of the present invention, FIGS. 2 and 3 are timing diagrams for explaining the operation of the computer device, and FIG. 4 is an evacuation recovery in the computer device. FIG. 5, which is a diagram showing an example of instructions, is a block diagram showing the configuration of a computer device according to another embodiment of the present invention. 1... Instruction cache section, 2... Main memory, 3...
・Prefetch buffer, 4...Instruction decoder, 5.
・・Vibration register, 6・Instruction execution unit, 7・
. . . Register file section, 8 . . . Data cache section, 9 . . . Resource management section, 10. . . Save/recovery instruction insertion section. Applicant's agent Patent attorney Takehiko Suzue Figure 1 MI M2 M3 M4 M
5 M6 Figure 2 Figure 3 ['757G==11 Figure 4

Claims (4)

[Claims] (1) A means for storing instruction codes, a prefetch buffer for sequentially fetching instruction codes from this means, an instruction execution means for executing instructions fetched into this prefetch buffer, and storing an instruction execution result in this instruction execution means. In a computer device, the computer device is equipped with a register file that detects an empty cycle of an execution resource and instructs to save and restore the contents of the register file, and a resource management device that detects an empty cycle of an execution resource and instructs to save and restore the contents of the register file, and A save/recovery instruction that inserts register file save/recovery instructions into free cycles of execution resources.
A computer device comprising a recovery command insertion means. (2) The computer device according to claim 1, wherein the resource management means detects an empty cycle of the execution resource based on information from the prefetch buffer. (3) The computer device according to claim 1, wherein the resource management means detects an idle cycle of the execution resource based on information from the instruction code storage means. (4) The instruction execution means includes an instruction decoder that interprets the instruction code from the prefetch buffer, and the save/recovery instruction inserting means inserts the save/recovery instruction into the instruction decoder. A computer device according to claim 1.