JPH01120129A - Programmable variable decoder circuit - Google Patents

Abstract

PURPOSE:To vary the decoder value of a decoder output by providing a decoder which outputs a pulse signal from a specified output terminal, latch circuits which hold specified address signals and coincidence detecting circuits. CONSTITUTION:When output terminal specification information (a) is 1 and a specified address signal (b) is (m), a pulse signal is outputted from a specified output terminal of the decoder 5 by raising a write signal (c) and (m) which is signal (b) is latched in a latch circuit 6-1. Consequently, the output (d) of the circuit 6-1 becomes (m) and the coincidence detecting circuit 7-1 detects whether or not an input address signal (e) coincides with the output (d). when the signal (e) is (m), the circuit 7-1 detects whether or not the signal (e) coincides with respective address values (m) of the output (d) and an output (f) goes up to high level and is outputted from an output terminal 8-1 Thus, (n) outputs (f) of (n) coincidence detecting circuits 7-0-7-n are used as (n) decoder outputs to output a pulse signal when the signal (e) has an optional address value.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a programmable variable decoder circuit that can be used in digital devices that require variable decoder values by external control, and particularly relates to a programmable variable decoder circuit that uses a counter output with a fixed phase as an input address signal. The present invention relates to a programmable variable decoder that is effective for multiplex type digital communication devices that require variable decoder values depending on the situation.

[Prior Art] Conventionally, this type of decoder did not exist, and only a fixed type decoder had a decoder output terminal corresponding to the address value of an input address signal.

[Problems to be Solved by the Invention] The conventional fixed type decoder described above has an output terminal corresponding to an address value, and due to the limitation of the output terminal section, the input address signal has about 3 to 4 inputs. With something that
Since it is implemented as a single-chip IC, it has the disadvantage that it cannot be used for a device with a large number of input address signals. Therefore, in order to configure a conventional decoder with a large number of decoders, it is necessary to invert any plurality of input address signals, use a multi-input AND gate or a Nant gate, realize it by a combination of multiple ICs, or use a read-on memory. Although it is possible to use methods such as using it as a decoder,
In any case, the disadvantage is that it is not possible to configure the decoder value to be externally variable.

[Means for Solving the Problems] An object of the present invention is to solve the above-mentioned problems and provide a programmable variable decoder circuit in which a decoder value can be changed externally as required.

In order to achieve the above object, the programmable variable decoder circuit according to the present invention is a programmable variable decoder circuit that outputs a pulse signal at an arbitrary address value of an input address signal, and for specifying the output terminal from n output terminals. A decoder that outputs a pulse signal from a designated output terminal by inputting a write signal for writing an output terminal designation information and an address value, and a pulse signal that outputs a designated address signal that specifies an address value from the output terminal. n latch circuits that hold based on the signal; and n match detection circuits that detect a match between the input address signal and the designated address signal held by the latch circuit, and output a pulse signal based on the detection result. It is constructed by providing.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a programmable variable decoder circuit according to an embodiment of the present invention.

In the figure, the programmable variable decoder circuit according to the present embodiment has an input terminal 2 to which output terminal designation information a that designates the output terminal of the decoder 5 is input, and an input terminal to which a write signal C for writing an address value is input. 4, a decoder 5 outputs a pulse signal from output terminals (n pieces) according to the output terminal designation information a and the write signal C, an input terminal 3 that inputs a designation address signal S designating an address value, and a designation n latch circuits 6 that hold the address signal by pulse signals generated from the decoder 5
-0 to 6-n, the input address signal e input from the input terminal 1 and the output d from the latch circuits 6-0 to 6-n are detected, and the detection results are sent to the output terminals 8-0 to 6-n. 8-n
It is composed of n coincidence detection circuits 7-0 to 7-n that output from the same circuit.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 and 3.

2 and 3 are timing diagrams showing the operation of the programmable variable decoder circuit of FIG. 1.

For example, as shown in FIG. 2, output terminal designation information a is set to “
1" and the designated address No. 13 is "m", a pulse signal is output from the designated output terminal by raising the write signal C, and the designated address signal No. 13 is "m" to the latch circuit 6-1. '' is latched. Therefore, the output d of the latch circuit 6-1 becomes "m", and the -number output circuit 7-1 outputs the input address signal e and the output d latched by the latch circuit 6-1. Detect whether there is a match or not.

When the input address signal e is "m", as shown in FIG. Circuit 7-
1's output f becomes high level and is output from the output terminal 8-1.

In this way, by setting the n outputs f of the n coincidence detection circuits 7-0 to 7-n as 0 decoder outputs, a pulse signal can be output at any address value of the input address signal e. Can be done.

[Effects of the Invention] As explained above, the present invention allows the decoder value of the decoder output to be varied as necessary, and by providing the minus number output circuit, the number of input address signals can be increased. This is also a circuit that can be integrated into an IC.

In addition, by realizing it with an LSI of 50 to 70 bins,
It has an effect that can be used for all digital devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a programmable variable decoder circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams showing the operation of the programmable variable decoder circuit of FIG. 1. 1.2, 3, 4: Input terminal 5: Decoder 6-0 to 6-n: Latch circuit 7-0 to 7-n Match detection circuit 8-0 to 8-n: Output terminal a: Output terminal designation information Second finger chamber address signal C: Write signal d: Latch output e: Input address signal

Claims (1)

[Claims] In a programmable variable decoder circuit that outputs a pulse signal when an input address signal has an arbitrary address value, output terminal designation information and address value for designating the output terminal from n output terminals are written. a decoder that outputs a pulse signal from a designated output terminal by inputting a write signal for the purpose, and n latch circuits that hold a designated address signal with a designated address value based on the pulse signal output from the output terminal. and n coincidence detection circuits that detect coincidence between the input address signal and the specified address signal held by the latch circuit, and output a pulse signal based on the detection result. Programmable variable decoder circuit.