JPH01179435U - - Google Patents

Info

Publication number
JPH01179435U
JPH01179435U JP1988076511U JP7651188U JPH01179435U JP H01179435 U JPH01179435 U JP H01179435U JP 1988076511 U JP1988076511 U JP 1988076511U JP 7651188 U JP7651188 U JP 7651188U JP H01179435 U JPH01179435 U JP H01179435U
Authority
JP
Japan
Prior art keywords
semiconductor chip
printed wiring
integrated circuit
circuit device
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988076511U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988076511U priority Critical patent/JPH01179435U/ja
Publication of JPH01179435U publication Critical patent/JPH01179435U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例を示す複合集積回路
装置の半導体チツプを含めたプリント配線基板の
部分断面図である。 1……プリント配線基板、2……アルミナセラ
ミツク板、3……半導体チツプ、4……抜け穴、
5……配線、6……金属細線、7……窪み部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子が形成された半導体チツプをプリン
    ト配線基板に搭載してなる複合集積回路装置にお
    いて、一表面に抜け穴を有する窪みが形成された
    前記プリント配線基板と、前記窪みに埋設された
    前記半導体チツプと同程度の大きさのアルミナセ
    ラミツク板と、前記アルミナセラミツク板に搭載
    された前記半導体チツプとを備えることを特徴と
    する複合集積回路装置。
JP1988076511U 1988-06-08 1988-06-08 Pending JPH01179435U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988076511U JPH01179435U (ja) 1988-06-08 1988-06-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988076511U JPH01179435U (ja) 1988-06-08 1988-06-08

Publications (1)

Publication Number Publication Date
JPH01179435U true JPH01179435U (ja) 1989-12-22

Family

ID=31301534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988076511U Pending JPH01179435U (ja) 1988-06-08 1988-06-08

Country Status (1)

Country Link
JP (1) JPH01179435U (ja)

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