JPH01228060A - Fft arithmetic unit - Google Patents

Abstract

PURPOSE:To shorten an FFT (Fast Fourier Transform) operation time by successively storing an A/D-converted data in a storing part and reading at a high speed and using them from latest data retroactively to the past with the timing of FFT operation. CONSTITUTION:An input signal lambda, after it passes through an LPF 1 and a sample holder 2, is digitized by an A/D converter 30. The value is written to the address of a storing part 6 instructed by an address preparing part 7 composed of an up-counter. At the time of starting the FFT, the counted value of the address preparing part 7 is shifted to an address preparing part 9 composed of a down-counter by the signal from a timing controller 10. Next, the address preparing part 9 is decremented at a high speed, the contents of the storing part 6 of the corresponding address are read to an FFT converting part 8 and the FFT conversion is executed.

Description

[Detailed Description of the Invention] <Industrial Field of Application> The present invention provides an input signal that is an observed waveform in an arithmetic unit.
T (Fast Fourier Transfer
m) FFT calculation unit for calculation! In particular, the arithmetic unit is a DSP (Digital Signal Processor).
The present invention relates to an improvement of an FF'l' arithmetic device which is configured with FF'l' (sor) etc. and performs FFT calculation in real time to shorten the response time.

<Prior art> Conventionally known technologies of this type include, for example, "Waveform Data Processing for Scientific Measurement J" (CQ Publishing Co., Ltd., 1932).
3rd edition published on November 30, 1999).

FIG. 3 is a block diagram of a conventional FFT calculation device.

In FIG. 3, λ is, for example, an analog input signal with an observed waveform that is normally a signal consisting only of random noise and includes a specific frequency at a certain time. This input signal λ is applied to a low-pass filter (hereinafter rLPFJ), for example.
(hereinafter referred to as "rS/H circuit") 1 is sampled by a sample hold circuit (hereinafter referred to as "rS/H circuit") 2, and then digitally converted by an analog-to-digital conversion circuit (hereinafter referred to as "FAT C circuit") 3. be done. The digitally converted data is led to the calculation unit 4 and stored in the storage unit (RAM).
The written data is stored (written) in the FFT calculation section (rDsP hereinafter) 42, which is composed of a system such as a DSP, which is made up of a microcomputer, etc., and reads out, calculates, and analyzes the written data in real time. F
'I' is calculated, the specific frequency is detected, and a detection signal is output.

This detection signal is displayed in a predetermined manner on the display section 5, for example.

By the way, in order to perform calculations in real time with the DSP 42, the storage section 41 is usually composed of a pair of RAMs (random access memories) 41a and 41b, as shown in FIG. 4 (a diagram used to explain the conventional technology). So, one RA
When M (here, #1RAM41a) is in the process of writing, the data written to the other RAM (here, #2RAM41b) is read and used, and conversely, the other #2RAM41b is in the process of writing. In the case of one #l
Normally, the configuration is such that the continuity of calculations is ensured by disposing changeover switches 41c and 41d, which operate alternately and reversely to read data from the RAM 41a. (See No. 55-122178).

Therefore, the operation when FIG. 5 is combined with FIGS. 3 and 4 will be described below using FIG. 5, which shows a time chart.

In FIG. 5, <1) is the input signal λ. This input signal λ represents a state in which a specific frequency component is generated at time t4 and the amplitude increases. (I+) is #lRAM41
represents the time transition of data writing to a (for example, the number of data is determined by the sampling time, such as 512 data), m represents the transition of data writing time to #2 RAM 41b, (trans) represents the data processing of the DSP 42 (
(V) represents the timing at which a specific frequency component that occurred in the input signal λ at time t4 can be detected at time t7.As can be seen from this time chart, the specific frequency component actually The time required from the occurrence of the detection signal to the output of the detection signal is #2RAM41
Time difference T1 between the time until the required number of data is written to FF 'l' and the timing at which a specific frequency occurs
(times t4 to ts) and the time 'r2 (times ta to tv) required for reading the data written to this #2 RAM 41b into the DSP 42 and performing the FFT calculation, at time t7, the detection signal (specific frequency This means that a signal indicating, for example, the time when the signal was received, is obtained.

<Problem to be solved by the invention> At this time, if the calculation time in the DSP 42 is slower (longer) than the time required for the FFT calculation to be collected in one RAM, the same problem does not arise. DSP
If the FFT calculation processing time of 42 is faster (shorter) than the time to write data to one RAM, 'I'1+
Time t at T2! The period from 1 to t6 is wasted time. That is, there is a problem in that the detection time is delayed by this dead time and is output.

The present invention has been made in view of the problems of the conventional technology, and is independent of the time required for the data necessary for the FPT calculation to be collected in the storage unit in relation to the FFT calculation processing time. It is an object of the present invention to provide an improved F F T calculation device that increases the number of calculations performed by a calculation unit in a certain period of time and speeds up the response time to changes in input signals.

Means for Solving the Problems> To achieve the above object, the present invention provides an FFT calculation device that converts an analog input signal into a digital signal and stores it, and performs an FFT calculation on the stored data in a calculation unit. a storage section that sequentially stores the digitally converted data and can read out asynchronously with the storage operation; and a write address generation section that generates an address signal for storing the digitally converted data in the storage section. a read address generation section that generates an address signal for reading data stored in the storage section backwards from the latest data asynchronously with the storage operation; an analog-to-digital conversion circuit; and the write address generation section. and a timing controller to which a signal from the arithmetic unit is guided to determine the timing of the operation of the write address generation unit, the read address generation unit, and the storage unit. It is characterized by:

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings. In the following drawings, parts that overlap with those in FIGS. 3 to 5 are given the same numbers, and the explanation thereof will be omitted.

FIG. 1 is a block system diagram of an FFT calculation device that is a specific embodiment of the present invention.

In FIG. 1, 30 is an ADC circuit that digitally converts the analog input signal after sampling. 6 is F
Storage unit for input storage in FT calculation (waveform storage element)
The storage section 6 is composed of, for example, a dual port memory (DualPort RAM, hereinafter referred to as rDPRAM), which sequentially stores waveform data converted into digital data by the ADC circuit 30 and can be read out asynchronously separately from this storage operation. In order to make this DPRAM6 function,
A write address generation unit (hereinafter referred to as up counter) 7, which is composed of an up counter, generates and outputs a write address signal for writing the digitally converted data to the DPRAM 6, and A read address generation unit (hereinafter described as a down counter) 9 consisting of a down counter, for example, generates and outputs an address signal for reading data to the DSP 8 from the latest data backwards, asynchronously with the write operation by the up counter 7. and inputs the signal from the DSP 8, and also inputs the signal from the ADC circuit 3.
0. Up counter 7, down counter 9 and DPRA
A timing controller 10 that determines the timing of the operation of M6 is provided.

As a result, the number of data required for FFT calculation is
Since it is possible to read the latest data from the RAM 6 into the DSP 8 in a chronologically backward manner at high speed, the analysis time is shorter than the conventional method of starting the FFT calculation after the necessary amount of data has been collected. It becomes possible to shorten the time.

FIG. 2 is a time chart for explaining the present invention.

The operation shown in FIG. 1 will be explained below using FIG. 2.

■: The input signal ([side waveform) λ] shown in Fig. 2 (1) is A
It is digitally converted by the DC circuit 30, and the timing controller 10 synchronizes the conversion timing of the ADC 30 with the count operation of the up counter 7 (operation to determine the update timing of the address including ia), so that the DPRA is always
Written to M6. FIG. 2 (1i) is a diagram showing continuous writing timing to the DPRAM 6 with respect to the time axis, that is, low-speed writing by data sampling. The stored data at this time is written in order from the bottom as shown by the broken line α in DPRAMe in FIG. 1, and when the top row is incorrectly stored, the data is stored again from the bottom row while erasing the previously stored data.

(d) On the other hand, the DSP 8 outputs a trigger signal and a read signal to the timing controller 10 after the previous FFT calculation is completed.

(2): Upon receiving the signal from the DSP 8, the timing controller 10 sends a signal to the up counter 7, and controls the count value of the up counter 7 to be guided to the load input terminal of the down counter 9.

As a result, the latest data position in the DPRAM 6 is loaded into the down counter 9.

■: The down counter 9 counts down the latest stored data obtained from the value of the up counter 7 one count at a time using the read signal of the DSP 8.
8 to the DPRAM 8, the current latest stored data (for example, the DPR in FIG.
The area ψ) indicated by AM6 band is D P RAM in Fig. 1.
As shown by the arrow β in e, going back in the past, the required high-speed read data (for example, 512 data) by the DSP 8 from the DPRAM 6 in FIG. 2 (2) is sequentially read by the width δ. .

(2): Based on the latest information read, the DSP 8 continuously performs a, b, and c, like the continuous FFT operation of the DSP 8 shown in FIG.

Performs FFT calculation and analysis of ... and detects changes in frequency components in the input signal λ0For example, if the input signal λ contains a specific frequency at time t45 and the waveform changes,
This data at time t45 is subjected to the FFT operation by the DSP 8 because it is the data read from the DPRAM 6 between times t3 and t5.
9. For example, when conditions predetermined on the program are satisfied, the timing when a change in a specific frequency component can be detected is shown in FIG. 2 M based on the F F T calculation operation in is detected based on the comparison result with the determination level for determining that it is included, and at time t
A detection signal is output at step 6.

As a result of the above, at the detection time shown in Fig. 2, 'I' in Fig. 1 is
', +72.

For example, if the input signal λ in FIG. 1 is a signal obtained using a sensor that monitors mechanical vibrations, the occurrence of abnormal parasitic vibrations can be detected at high speed. In this way, the technique of the present invention can be used as a fail-safe function.

<Effects of the Invention> As described above, the present invention has been specifically explained along with the examples.
According to the F F 'l' arithmetic device of the present invention, the following effects can be achieved.

Conventionally, FF is performed after the required number of data for FFT calculation is collected.
Since we were calculating T, the time to detect the change in the signal we want to measure is ``Time required to collect data J + rFFTF
However, with the present invention, the time required for data collection can be read from the DPRAM at high speed, so it is substantially dependent only on the time required for FFT calculation, so it is much faster than before. The time required for detection can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of an FFT calculation device that is a specific embodiment of the present invention, FIG. 2 is a time chart for explaining the present invention, FIG. 3 is a block system diagram of a conventional FFT calculation device, and FIG. The figure is a diagram used to explain the conventional technique, and FIG. 5 is a time chart used to explain the operations shown in FIGS. 3 and 4. 1...Low pass filter (LPF), 2...Sample hold circuit (S/H circuit), 3.30...Analog-to-digital conversion circuit (ADO circuit), 6...Storage unit (
DPRAM), 7... Write address generation unit (up counter), 8... FFT calculation unit <DSP), 9...
・Read address generator (down counter), 10...
・Timing controller. Figure 2 Figure 3 Figure 4 Figure 5 (W) ノ17i;--ノ3-3;;--1---t'
(Ttt7z-@ (V)
--1tfu

Claims (1)

[Claims] An FFT arithmetic device that digitally converts and stores an analog input signal and performs an FFT operation on the stored data in an arithmetic unit; , a write address generation unit that generates an address signal for storing the digitally converted data in the storage unit; and a write address generation unit that generates an address signal for storing the digitally converted data in the storage unit; A read address generation section that generates an address signal to be read out, an analog-to-digital conversion circuit, and the write address generation section are timed, and a signal from the calculation section is guided to generate the write address. An FFT arithmetic device comprising: a timing controller for timing operations of the read address generating section and the storage section;