JPH0128948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field memory read control circuit, and in particular to a field memory used when displaying a moving image by supplying data recorded in the field memory to a cathode ray tube display device using interlace scanning. This relates to a read control circuit.

When displaying data recorded in the field memory on a cathode ray tube display device using interlace scanning, the contents are read out while sequentially shifting the memory addresses of the field memory in synchronization with the scanning lines of the cathode ray tube display device. We are supplying When displaying the data recorded in the field memory as a still image, for example, the data recorded at each address of the field memory shown in Figure 1 can be displayed in the upper left corner (usually this is the "0" address). ) and display them sequentially. In other words, if the addresses in the Y and X directions are expressed as "XY", 00→01
→02→…0n→10→11→12→1n→20→21→22→…
If you read out in the order of 2n →...mn, the entire field memory will be displayed as a still image. On the other hand, if the readout start address is started from the middle instead of from "0", the display position of the still image will be shifted. For example, if you start the address in the Y direction from "4" instead of "0", the address YX will be 40.
Since the data is read out in the order of →41→42→...5n→51→52→...5n..., the display pattern is shifted upward as shown in FIG.

Therefore, the start address in the Y direction is changed from 0 → 1 →
By sequentially shifting 2 → 3 →..., Figure 3 a to c
The display screen will scroll upwards as shown.
That is, by sequentially incrementing or decrementing the read start address of the field memory, a still image can be moved and a moving image display can be performed. This also applies to the X direction.

Next, a cathode ray tube display device that displays an output signal from a field memory generally performs interlace scanning in which odd fields and even fields are alternately scanned. Therefore, depending on the timing of changing the read start address of the field memory, flickering may occur on the display screen. This flickering will be explained below.

First, the memory configuration in the Y direction is set to 2 scanning lines (2 fields) for 1 address, or 1 dot, and
It is assumed that the change timing with respect to the start address in the direction is a vertical scanning period (approximately 1/3 second), and one dot is updated every two vertical scanning periods. Here, when moving the screen downward (method of decrementing the start address), we will consider the case where the change timing of the start address is set to an odd number field and the case where it is set to an even number field. In interlaced scanning, the scanning lines of the odd field are illuminated first, and then the scanning lines of the next even field are illuminated. Therefore, the fourth
If the pattern shown in the figure (a pattern with dots displayed only in the center of the screen) is moved downward, and the start address is changed in an odd field, the time during which the scanning line lights up will be as shown in Figure 5a. Since the target timing matches the moving direction of the screen, the display screen can be smoothly moved and displayed. On the other hand, when the start address is changed in an even field, as shown in Figure 5b, the screen moves in the opposite direction (downward) after the even field's scanning line lights up. Odd scanning lines will be illuminated. Then, in the subsequent even fields, there will be an interval of two scanning lines. Therefore, visually, it appears as if a shutter or a missing line has occurred at the edge of the display pattern, making it impossible to display the display screen moving smoothly. A similar problem also occurs when the start address is changed in an odd field when the screen is moved upward. This problem involves 2 dots (scanning line 4) in 2 vertical scanning periods.
If the display screen is moved over the course of the main task, the above phenomenon becomes even more significant. and,
Although the above explanation is an example of the most extreme case, a similar problem naturally occurs even when the start address is changed asynchronously with respect to vertical scanning, depending on the timing. Note that a similar phenomenon occurs in the X direction, but since the horizontal scanning period is considerably faster than the vertical scanning period, it is not visually noticeable.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a field memory readout control circuit that prevents disturbances in the display screen when moving and displaying the recorded contents of the field memory in the vertical direction. below,
A field memory read control circuit according to the present invention will be explained in detail using the drawings.

FIG. 6 is a circuit diagram showing an embodiment of a field memory read control circuit according to the present invention. In the figure, reference numeral 1 denotes a central processing unit, which inputs a vertical synchronizing signal of a cathode ray tube display device (not shown) as an interrupt signal to port _P1 , and generates a write signal from port _P2 . 2 is an address bus from central processing unit 1
A decoder that decodes the address signal supplied via AB and outputs an address enable signal; 3 is a NAND gate that receives the write signal and address enable signal; 4 is supplied from the central processing unit 1 via the data bus DB a Y-direction start address set register which sets the Y-direction start address signal to be generated when the output of the NAND gate 3 is generated; 5 is a latch circuit whose input is the output of the Y-direction start address register 4;
is preset by the output of the latch circuit 5, and the Y direction address is determined by counting the horizontal synchronizing signal HS.
A Y-direction display address counter supplies YA and an X-direction address XA generated from an X-direction display address counter (not shown) to the field memory 7 for reading, and 8 is a Y-direction display address counter that supplies the output and input of the latch circuit 5 to the A and B inputs, respectively. The comparator is constructed so that when A>B, a comparison output K is generated, and when A<B, a comparison output L is generated. 9 is a capacitor that delays the vertical synchronizing signal VD to some extent and supplies it to the inverter 10; 11 is a flip-flop circuit that is set or reset depending on the state of the horizontal synchronizing signal HS when the output of the inverter 10 is generated; 12 is a flip-flop circuit that supplies the output of the inverter 10; 13 is an AND gate which receives the discrimination output L, the output signal of the inverter 12, and the set output Q of the flip-flop circuit 11; 14 has the reset output of the flip-flop circuit 11, the output of the inverter 12, and the comparison output K as inputs; And gate, 1
Differentiating circuits 5 and 16 differentiate the outputs of the AND gates 13 and 14 to generate a rising differential output, and the output signals thereof are supplied to the latch circuit 5 via an OR gate 17 as a clock signal.

In a circuit configured in this manner, the vertical synchronizing signal VD shown in FIG. 7a and the horizontal synchronizing signal VD shown in FIG. 7b are synchronized in odd fields, but in even fields. Horizontal sync signal
The signal starts from the middle part of HD. Therefore, by slightly delaying the vertical synchronizing signal in the capacitor 9 as shown in FIG.
Horizontal synchronization signal when this clock signal is generated
When the state of HS is latched, the set output signal Q becomes "L" in odd fields and "H" in even fields, as shown in FIG. 7d. Therefore, by knowing the state of the output signal Q of the flip-flop circuit 11, it is possible to determine whether the display field at the present time is an odd number or an even number.

Next, when the vertical synchronization signal is generated, the central processing unit 1 enters the interrupt mode, an address signal designating the Y-direction start address set register 4 is generated, and the decoder 2 generates an address enable signal. In addition, in order to generate a write signal from output port _P2 in the interrupt mode, central processing unit 1 generates an output from NAND gate 3 and sets the updated Y-direction start address in Y-direction start address set register 4. be done. In this state, the update Y-direction start address is supplied to the input side of the latch circuit 5.
Furthermore, the Y-direction start address of the currently displayed screen is output to the output side of the latch circuit 5. Therefore, by comparing the input signal and output signal of this latch circuit 5 in the comparator 8, the moving direction of the screen can be determined. That is, when the screen is moved upward, the comparison output L becomes "H" as shown in FIG. 7e.
As shown in FIG. 7e, when the screen is set to move upward in an odd field, at the time the central processing unit 1 sets data in the Y direction start address set register 4 The "L" of the comparison output K of the comparator 8 becomes "H", but since the set output Q of the flip-flop circuit 11 is "L", the output of the AND gate 13 becomes "L". It cannot be set to “H”. Therefore, the re-latching operation of the latch circuit 5 is prevented, and the updated Y direction start address is stored in the Y direction display address counter 6.
This prevents the display from being distorted due to being set to . Then, when moving to the next field, it becomes an even field and the set output Q of the flip-flop circuit 11 becomes "H". Further, when the output signal of the inverter 12 becomes "H" as shown in FIG. 7f, the output of the AND gate 13 momentarily becomes "H" as shown in FIG. 7g. The rising portion of the output signal of the AND gate 13 is differentiated in the differentiating circuit 15 as shown in FIG. The latched output signal becomes the update Y direction start address as shown in FIG. 7i. Furthermore, when the latch circuit 5 is relatched, the A and B inputs of the comparator 8 become the same, so that the "H" output of the comparison output K is returned to "L". and,
When the latch circuit 5 is relatched, the updated Y direction start address is preset in the Y direction address counter 6 as shown in FIG.
It is counted every time HD occurs, and the Y-direction address YA for the field memory 7 is sequentially changed.

The above explanation is based on the case where the data is set to move the screen upward in an odd number field, but the explanation of each part when the data is set to move the screen downward in an odd number field is as follows. The waveforms are as shown in FIGS. 7j to n. In other words, in an odd field, the flip-flop circuit 1
The reset output of 1 is “H” as shown in Figure 7j.
It is becoming. On the other hand, when the update Y-direction start address is specified to move the screen downward, the comparison output K of the comparator 8 is
It becomes "H" as shown in Figure k. When the comparison output K becomes "H", the output of the AND gate 14 becomes "H" during the "L" period of the horizontal synchronization signal when the generation of the vertical synchronization signal ends, as shown in FIG. The rising portion of the output signal of the AND gate 14 generated in the above manner is differentiated in the differentiating circuit 16 and outputted as a narrow signal shown in FIG. Since the signal relatches the latch circuit 5 via the OR gate 17, the updated Y direction start address is latched into the latch circuit 6 as shown in FIG. In other words, in the circuit with the above configuration, when the comparator 8 detects that the screen moves upward,
When the flip-flop circuit 11 detects an even field, the update Y-direction start address is set, and when the comparator 8 detects that the screen moves downward, the flip-flop circuit 11 sets the start address in the Y direction when it detects an odd field. This means that the update Y-direction start address is set to prevent screen disturbances.

As explained above, according to the field memory read control circuit according to the present invention, when displaying a screen that moves in the vertical direction using the output signal of the field memory, it is possible to set the update Y-direction start address without disturbing the screen. This has an excellent effect in that conditions that do not occur can be automatically determined and preset in the Y-direction display address counter.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of pattern recording in the field memory, Fig. 2 is a diagram showing an example of display when reading with changing Y direction start address, Fig. 3 a-
c is a diagram showing a display example when the Y-direction start address is changed sequentially in field units; FIGS. FIG. 6 is a circuit diagram showing an embodiment of a field memory read control circuit according to the present invention, and FIGS. 7 a to 7 n are operation waveform diagrams of each part of the circuit shown in FIG. 6. 1...Central processing unit, 2...Decoder, 3
...NAND gate, 4...Y direction start address set register, 5...Latch circuit, 6...Y
Direction display address counter, 7... Field memory, 8... Comparator, 9... Capacitor,
10, 12... Inverter, 11... Flip-flop circuit, 13, 14... AND gate, 1
5, 16... Differential circuit, 17... OR gate.

Claims (1)

[Claims] 1. A Y-direction start address set register to which the Y-direction start address to be updated is supplied;
A latch circuit which receives the output of this Y-direction start address set register as an input, and a Y-direction circuit whose output signal is set and which counts horizontal synchronizing signals of a cathode ray tube display device by interlace scanning.
A direction display address counter, a field memory in which a Y direction address is designated by the output of this Y direction display address counter, and a comparator that determines the moving direction of the screen in the vertical direction by comparing the input and output of the latch circuit. and,
A flip-flop circuit which uses the vertical synchronizing signal of the cathode ray tube display device as a clock input with a slight delay and determines whether the field is odd or even at the present time by latching the horizontal synchronizing signal when the clock input is generated. , when the comparator detects an upward screen movement, it latches the latch circuit when an even field detection signal is output from the flip-flop circuit, and when it detects a downward screen movement, it latches the odd field. 1. A field memory read control circuit comprising: a gate circuit for latch-controlling the latch circuit when a field detection signal is output.