JPH01307219A - Electrode forming method for semiconductor device - Google Patents
Electrode forming method for semiconductor deviceInfo
- Publication number
- JPH01307219A JPH01307219A JP13784388A JP13784388A JPH01307219A JP H01307219 A JPH01307219 A JP H01307219A JP 13784388 A JP13784388 A JP 13784388A JP 13784388 A JP13784388 A JP 13784388A JP H01307219 A JPH01307219 A JP H01307219A
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- vacuum
- silicon substrate
- eutectic
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000005496 eutectics Effects 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 8
- 239000000956 alloy Substances 0.000 claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 claims abstract description 7
- 229910052737 gold Inorganic materials 0.000 claims abstract description 7
- 239000010931 gold Substances 0.000 claims abstract description 7
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052732 germanium Inorganic materials 0.000 claims abstract 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract 3
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 2
- 230000007797 corrosion Effects 0.000 abstract description 7
- 238000005260 corrosion Methods 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000007738 vacuum evaporation Methods 0.000 abstract description 5
- 238000001704 evaporation Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract description 2
- 238000005728 strengthening Methods 0.000 abstract description 2
- 230000001939 inductive effect Effects 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000009661 fatigue test Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- AADHKGMGPIHQPB-UHFFFAOYSA-N [V].[Cr].[Ni] Chemical compound [V].[Cr].[Ni] AADHKGMGPIHQPB-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010587 phase diagram Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Landscapes
- Die Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特に比較的大きな電力を扱う電力
用半導体装置の電極形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming electrodes of semiconductor devices, particularly power semiconductor devices that handle relatively large amounts of power.
従来の技術
従来、電力用半導体装置の電極形成方法としては、パワ
ートランジスタを例にして説明すれば、エミッタ及びベ
ース電極はアルミニウム蒸着膜が、また、コレクター電
極にはAu−3i合金またはニッケルバナジウムクロム
等の遷移金属が広く用いられていた。BACKGROUND OF THE INVENTION Conventionally, as a method for forming electrodes of power semiconductor devices, taking a power transistor as an example, the emitter and base electrodes are formed using an aluminum evaporated film, and the collector electrode is formed using an Au-3i alloy or nickel vanadium chromium. Transition metals such as these were widely used.
電力用半導体装置の電極形成において留意すべき点は、
半導体装置の使用中、しばしば電極材料の乾腐食が発生
し熱抵抗を増大させたり、また断線不良を発生させたり
することを防ぐことが重要である。この現象は一般的に
「熱疲労現象」七呼ばれている。Points to keep in mind when forming electrodes for power semiconductor devices are:
During use of a semiconductor device, it is important to prevent dry corrosion of electrode materials that often occurs, increasing thermal resistance and causing disconnection defects. This phenomenon is generally called the "thermal fatigue phenomenon".
特に樹脂封止型半導体装置においてはハーメチック型半
導体と比較して乾腐食が発生しゃすく信頼性を悪くして
いた。このような乾腐食を防ぐため、電極構造、電極材
料、封止材料、接着工程等の改善がなされている。In particular, in resin-sealed semiconductor devices, dry corrosion is more likely to occur than in hermetic semiconductor devices, resulting in poor reliability. In order to prevent such dry corrosion, improvements have been made to electrode structures, electrode materials, sealing materials, bonding processes, and the like.
発明が解決しようとする課題
本発明は、乾腐食(熱疲労現象)を遅延させ高信頼性の
電力用半導体装置の電極形成方法を提供する。Problems to be Solved by the Invention The present invention provides a method for forming electrodes of a highly reliable power semiconductor device by delaying dry corrosion (thermal fatigue phenomenon).
従来、シリコン基板に電極を形成させる場合、シリコン
基板上に真空蒸着で金属膜を付着した後、次いで熱処理
を行い、共晶化もしくは化合させる方法が多い。この場
合真空蒸着後熱処理を施す迄に時間がかかり、表面が酸
化したり、取り扱い方で傷などを発生させ、均一な接着
力を得られない欠点があった。その為酸化している箇所
や傷などを基点として一層酸化が進行し乾腐食を促進さ
せていた。Conventionally, when forming an electrode on a silicon substrate, there are many methods in which a metal film is deposited on the silicon substrate by vacuum evaporation, and then heat treatment is performed to form eutectic or combine the metal film. In this case, it takes time to perform heat treatment after vacuum deposition, and the surface may be oxidized or scratches may occur due to handling, resulting in the disadvantage that uniform adhesion cannot be obtained. As a result, oxidation progressed further starting from oxidized areas and scratches, promoting dry corrosion.
課題を解決するための手段
このような問題点を解決するため、本発明では第一の金
属膜を真空蒸着によってシリコン基板上に付着させる際
、シリコン基板を340℃から400℃に高めておくこ
とにより、真空蒸着と同時に共晶化反応もしくは化合反
応をおこさせ、それによりシリコン基板と第一金属膜と
の間を強力にしようとするものである。金属膜は真空中
で気化されているため、活化されており状態図で示され
る共晶温度及び化合温度よりもかなり低温で共晶や化合
をおこすことができる。この後続けて第二の金属膜を真
空蒸着しリードフレームとのはんだづけを容易にさせる
のである。Means for Solving the Problems In order to solve these problems, in the present invention, when the first metal film is deposited on the silicon substrate by vacuum evaporation, the temperature of the silicon substrate is raised from 340°C to 400°C. This is intended to cause a eutectic reaction or a combination reaction simultaneously with vacuum evaporation, thereby strengthening the bond between the silicon substrate and the first metal film. Since the metal film is vaporized in a vacuum, it is activated and can undergo eutectic and combination at a temperature considerably lower than the eutectic and combination temperatures shown in the phase diagram. Subsequently, a second metal film is vacuum deposited to facilitate soldering to the lead frame.
従って第二の金属膜としてはニッケルや銀など、はんだ
材と接着しやすい金属が適する。Therefore, a metal that easily adheres to the solder material, such as nickel or silver, is suitable for the second metal film.
作用
本発明によると、低温で第一金属膜とシリコン基板との
合金化が達成され、安定性の高いコンタクト電極形成が
実現できる。According to the present invention, alloying of the first metal film and the silicon substrate is achieved at low temperatures, and highly stable contact electrode formation can be realized.
実施例
実施例1
パワートランジスタを例にして本発明の詳細な説明する
。Embodiments Embodiment 1 The present invention will be explained in detail using a power transistor as an example.
すでに全ての拡散処理が終了しエミッタ及びベースの各
電極にはアルミニウム膜を形成しであるシリコン基板を
真空蒸着槽内で340℃に加熱、Au−Ge合金(Ge
含有量15%)を厚み1.2μm蒸着させた。シリコン
と金の共晶温度は370℃であるが、340℃でも蒸着
中にシリコン基板と金とが共晶化反応をおこしているこ
とが、蒸着後の膜状態から理解できる。しかるのち第二
の金属膜としてクロム/クロムニッケル合金(Ni含有
量35%)/ニッケルをそれぞれ0.05μm、0.1
μm、0.3um連続蒸着した。All diffusion processes have already been completed and aluminum films have been formed on the emitter and base electrodes.The silicon substrate is heated to 340°C in a vacuum evaporation tank to form an Au-Ge alloy (Ge).
(content 15%) was deposited to a thickness of 1.2 μm. The eutectic temperature of silicon and gold is 370° C., but it can be understood from the state of the film after vapor deposition that even at 340° C., a eutectic reaction occurs between the silicon substrate and gold during vapor deposition. Thereafter, as a second metal film, chromium/chromium-nickel alloy (Ni content 35%)/nickel was deposited with a thickness of 0.05 μm and 0.1 μm, respectively.
um and 0.3 um were continuously deposited.
実施例2
実施例1と同じシリコン基板を400℃に加熱し、Au
−Ge−8b合金(Ge含有量15%。Example 2 The same silicon substrate as in Example 1 was heated to 400°C, and Au
-Ge-8b alloy (Ge content 15%.
sb含有量1.5%)を厚み2.0μm蒸着させた。し
かるのち第二の金属膜としてクロム/クロムニッケル合
金(Ni含有量35%)をそれぞれ0.05μm、0.
1μm、0.3μm連続蒸着した。sb content 1.5%) was deposited to a thickness of 2.0 μm. Then, as a second metal film, chromium/chromium-nickel alloy (Ni content 35%) was deposited with a thickness of 0.05 μm and a thickness of 0.05 μm, respectively.
Continuous deposition of 1 μm and 0.3 μm was performed.
このように電極形成の終了した基板から各チップに分割
しP b / S nを用いてTO220型のリードフ
レームに接着した。ワイヤーボンド、次いで、樹脂封止
したのち、熱抵抗による乾腐食テストを行った。熱疲労
させる条件は、半導体チップ1:5W (1=5A、V
=IA)をオン/オフ5分の間欠的に印加した。(この
時の温度差は105℃であった。オン時130℃、オフ
時25℃)第1図には本発明法(実施例1及び2)と従
来法(第一の金属膜を基板150℃で真空蒸着したのち
400℃に加熱し共晶化させた後、次いで第二の金属膜
を付着形成させたもの)との熱疲労テスト結果を示す。The substrate on which the electrodes had been formed was divided into chips and adhered to a TO220 type lead frame using Pb/Sn. After wire bonding and resin sealing, a dry corrosion test using heat resistance was conducted. The conditions for thermal fatigue are: semiconductor chip 1:5W (1=5A, V
=IA) was applied intermittently for 5 minutes on/off. (The temperature difference at this time was 105°C. 130°C when on, 25°C when off.) Figure 1 shows the method of the present invention (Examples 1 and 2) and the conventional method (the first metal film was The results of a thermal fatigue test are shown below for a sample obtained by vacuum evaporating at 400° C., heating to 400° C. for eutectic formation, and then depositing a second metal film.
結果は熱抵抗の変化とオン/オフの間欠回数で示した。The results were shown as changes in thermal resistance and number of on/off cycles.
従来法では約20000サイクルから熱抵抗が増加し、
劣化が観察されるのに対し、本発明法では全く熱抵抗の
劣化がない。明らかに熱疲労寿命が長いことがわかる。In the conventional method, the thermal resistance increases after about 20,000 cycles,
In contrast to the observed deterioration, the method of the present invention causes no deterioration of thermal resistance at all. It is clear that the thermal fatigue life is long.
発明の詳細
な説明したように本発明によれば、従来法に比較し、高
い信頼性の半導体装置を得るばかりか、作業工程(熱処
理を不要にした)の削減を図ることもでき、製造上利点
が多い。As described in detail, according to the present invention, compared to conventional methods, it is possible not only to obtain a highly reliable semiconductor device, but also to reduce the number of work steps (heat treatment is no longer required), which improves manufacturing efficiency. There are many advantages.
第1図は本発の方法の効果を表す熱疲労テスト結果の特
性図である。
1・・・・・・実施例特性曲線、2・・・・・・従来例
′特性曲線。FIG. 1 is a characteristic diagram of thermal fatigue test results showing the effectiveness of the method of the present invention. 1...Example characteristic curve, 2...Conventional example' characteristic curve.
Claims (1)
ず、第一の金属膜として少なくとも金とゲルマニウムを
含む合金を真空蒸着して、蒸着中にシリコンと金の共晶
化反応を起こさせる工程と、次いで第二の金属膜として
少なくともニッケル単体、もしくはニッケルを含む合金
を蒸着する工程とが構成されることを特徴とした半導体
装置の電極形成方法。A step of first vacuum-depositing an alloy containing at least gold and germanium as a first metal film onto a silicon substrate heated from 340° C. to 400° C., and causing a eutectic reaction between silicon and gold during the deposition; 1. A method for forming an electrode for a semiconductor device, comprising the step of: then depositing at least nickel alone or an alloy containing nickel as a second metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13784388A JPH01307219A (en) | 1988-06-03 | 1988-06-03 | Electrode forming method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13784388A JPH01307219A (en) | 1988-06-03 | 1988-06-03 | Electrode forming method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01307219A true JPH01307219A (en) | 1989-12-12 |
Family
ID=15208113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13784388A Pending JPH01307219A (en) | 1988-06-03 | 1988-06-03 | Electrode forming method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01307219A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52144272A (en) * | 1976-05-27 | 1977-12-01 | Nec Home Electronics Ltd | Forming method of electrode in semiconductor device |
| JPS5521186A (en) * | 1978-08-03 | 1980-02-15 | Mitsubishi Electric Corp | Ohmic electrode material for p-type 3-5 families compound semiconductor and forming method of ohmic electrode |
| JPS6247150A (en) * | 1985-08-26 | 1987-02-28 | Sumitomo Electric Ind Ltd | Semiconductor device and its manufacturing method |
-
1988
- 1988-06-03 JP JP13784388A patent/JPH01307219A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52144272A (en) * | 1976-05-27 | 1977-12-01 | Nec Home Electronics Ltd | Forming method of electrode in semiconductor device |
| JPS5521186A (en) * | 1978-08-03 | 1980-02-15 | Mitsubishi Electric Corp | Ohmic electrode material for p-type 3-5 families compound semiconductor and forming method of ohmic electrode |
| JPS6247150A (en) * | 1985-08-26 | 1987-02-28 | Sumitomo Electric Ind Ltd | Semiconductor device and its manufacturing method |
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