JPH0158716B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sampling clock pulse generation circuit for sampling a data signal in an apparatus for receiving a digital signal in which a data signal is sent following a clock run-in signal.

In the present invention, the following explanation will be given by taking teletext broadcasting as a typical example of digital transmission.

In teletext broadcasting, a digital signal consisting of a pulse train of "0" and "1", that is, the electrical voltage is "low" or "high", is multiplexed onto the television signal during a part of the vertical retrace period. After receiving this multiplexed signal with a character multiplexing receiver, and extracting the digital signal and performing digital processing,
Characters and figures are displayed on the surface of the cathode ray tube.

Figure 1 is a configuration diagram showing 1H of multiplexed signals (H is the horizontal scanning period), and shows the color burst signal 1H.
After a certain period of time, a clock run-in signal 2 is sent, followed by a data signal 3. These transmission speeds (hereinafter referred to as bit rates) are determined by NHK.
(Japan Broadcasting Corporation) - 5.73Mb/S for C55 format
It is. The clock run-in signal consists of a repeating "low" and "high" pulse train, and in the case of the NHK-C55 system, it consists of 16 bits.
The frequency is 2.86MHz, i.e. the bit rate
It has a high frequency of 1/2 of 5.73b/S, and generates a sampling clock pulse for sampling the data signal 3 in synchronization with this clock run-in signal. Note that the data signal 3 is
It is an NRZ (non-return to zero) digital signal, and when the bit rate is 5.73 Mb/S, the width of one bit is 175 μS.

FIG. 2 shows a block diagram of a text multiplex transmitter/receiver, where A is a text multiplex transmitter and B is a text multiplex receiver. 4 is the tuner circuit or VIF circuit,
5 is a gate circuit that extracts only 1H of the 20H character multiplex position; 6 is a slicer circuit that slices the multiplexed signal at an amplitude level of 1/2; 7
8 is a sampling clock pulse generation circuit that generates sampling clock pulses based on the clock run-in signal 2; 8 is a circuit that samples data signals and converts serial signals into parallel signals; 9 is a digital signal processing circuit; 10 is a circuit that samples data signals and converts serial signals into parallel signals; The video processing circuit 11 is a cathode ray tube.

FIG. 3 is a diagram showing the timing of sampling clock pulse generation by a conventional sampling clock pulse generation circuit. The sampling clock pulse 1 is reset at the falling edge of the sampling clock pulse 12, and the period T of the sampling clock pulse 12 is changed from the reset position.
Sampling clock pulse 12 is reproduced from a position delayed by 1/2 of , and data signal 3 is sampled. In this case, the overall group delay characteristic of the tuner circuit or VIF circuit of the text multiplex transmitter A and text multiplex receiver B is a flat characteristic as shown in a in FIG. If the group delay amount DL is 0 in the range (4 MHz to 0 MHz in the figure), the data signal is sampled at the maximum point of the peak value of the data signal pulse as shown in a in FIG. 5, and there is no problem. In Figure 5,
Since the data signal can be expressed by a 1-bit rising pulse signal, only the 1-bit pulse waveform is shown.
However, the overall group delay characteristic between the tuner circuit and the VIF circuit of the text multiplex transmitter A and text multiplex receiver B shows that as the frequency band decreases below 2MHz, the amount of delay increases as shown in Figure 4b. In such a case, pre-cut distortion occurs in the data signal as shown in FIG. 5b, and the maximum point of the peak value is delayed. Incidentally, the clock line signal 2 at this time is a sine wave of approximately 2.86 MHz as shown in FIG. In FIG. 6, reference numeral 13 indicates a Fleming code, but since it has no significant bearing on the gist of the present invention, a description thereof will be omitted. 14 is a slice level when slicing is performed by the slicer circuit 6. The frequency of the clock run-in signal 2 is approximately
As it is clear from Figure 4 that the frequency is 2.86MHz,
It is not affected by group delay characteristics of 2 MHz or less, and the sampling clock pulse generated based on the clock run-in signal has almost no delay. Therefore, 2M
In the conventional method of sampling data signals using a sampling clock pulse generation circuit due to the group delay characteristic of Hz or less, a phase shift occurs between the maximum peak value of the data signal and the sampling clock pulse, resulting in a decrease in the eye height rate. descend.

The present invention has been made in view of the above-mentioned points, and includes a transmission line (in this case, a tuner circuit to a VIF circuit of a text multiplex transmitter A and a text multiplex receiver B).
This paper proposes a means to improve the drop in eye height rate caused by the group delay characteristics (frequency band 2MHz or less) of

The present invention will be explained below with reference to FIGS. 7 to 12. In the present invention, the overall circuit configuration of the character multiplexing transmitter/receiver is the same as that shown in FIG. 2, but the feature of the present invention lies in the sampling clock pulse generation circuit, and FIG. A block diagram of one embodiment of the block pulse generation circuit is shown, and FIG. 8 shows a time chart for explaining the block diagram of FIG. 7.

When the clock run-in signal A sliced by the slicer circuit 6 shown in FIG. 2 is input to the reset pulse generator 15, the first pulse (No. 1 ) rises, the reset pulse ○low rises and is reset.

On the other hand, the frequency of 14.3 MHz obtained from the crystal oscillator circuit 16 is converted into a 28.65 MHz pulse train signal ○C by a doubling circuit 17, and inputted to a bit synchronization circuit 18 which performs bit synchronization with the reset pulse ○RO and pulse train signal ○C. By doing so, the bit synchronization pulse ○2 which rises at the falling edge of the first pulse of the pulse train signal ○C from the rising edge of the reset pulse ○ro is inputted to the divide-by-5 circuit 19 together with the pulse train signal ○c. The output obtained by dividing the frequency of the pulse train signal ○C by 5 from the rising edge of the bit synchronization pulse ○D is inputted to the serial-to-parallel conversion circuit 8 shown in FIG. 2 as a sampling clock pulse ○H. At this time, the sampling clock pulse ○H falls at the fifth rise of the pulse train signal ○C, counting from the rising edge of the bit synchronization pulse ○D. The timing of the sampling clock ○H is such that the next rising edge of the clock pulse ○H can be sampled at the center of the clock run-in signal ○A.

As mentioned above, the sampling clock pulse generation circuit of the present invention generates the first clock run-in signal 2.
Since the sampling clock pulse 12 is generated based on the 1st rising edge, the group delay DL of the transmission path from the text multiplex transmitter to the tuner circuit or VIF circuit of the text multiplex receiver (in a frequency band of 2 MHz or less) increases, clock pulse 2
Precut distortion occurs at the first rising edge of , and the clock run-in signal 2 is delayed. this is,
Even though the frequency of the clock run-in signal 2 is 2.86 MHz, which is a value unrelated to the group delay characteristic, if we focus on the first pulse of the clock run-in signal 2, it is found that it is intermittent (for example, in the United States). This is because the character multiplex signal is a low frequency signal that is transmitted every odd field. Therefore, the maximum point of the peak value of the data signal 3 and the sampling clock pulse 12
Since both are delayed at the same time, the eye height rate is improved.

FIG. 9 shows the phase relationship between the sampling clock pulse and the data signal according to the present invention. Delay characteristics increase in the lower part of the frequency band (DL=
200ns), the phase relationship between the sampling clock pulse and the data signal is shown, and as mentioned above, the sampling clock pulse is always sampled near the maximum point of the peak value of the data signal. Recognize.

FIG. 10 shows the results of a computer simulation to compare the effects of the present invention with the conventional case. This is an eye pattern when the clock is reset at the 7th pulse, and FIG. 10b is an eye pattern when it is reset at the 1st pulse of the clock run-in signal by the sampling generation circuit of the present invention. The group delay characteristic of the transmission path at this time is shown in FIG. FIG. 12 is a graph showing the relationship between the group delay amount DL and the eye-height rate. A comparison with DL200ns shows a 15% improvement.

According to the sampling clock pulse generation circuit of the present invention, it is possible to improve the reduction in eye height ratio due to the group delay characteristic of the transmission line, and to improve the quality of digital transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram of 1H of multiplexed signals, FIG. 2 is a block diagram of a character multiplexing transmitter/receiver, and FIG. 3 is a diagram showing the timing of sampling clock pulse generation by a conventional sampling clock pulse generation circuit. Figure 4 is a diagram showing group delay characteristics, and Figure 5 is a diagram showing group delay characteristics.
A diagram showing the phase relationship between a data signal and a sampling clock pulse generated by a conventional sampling clock pulse generator, FIG. 6 is a waveform diagram of a clock run-in signal and a flemming code, and FIG. 7 is a diagram showing the sampling clock pulse of the present invention. A block diagram of the generation circuit, FIG. 8 is a time chart diagram for explaining the operation of the sampling clock pulse generation circuit of the present invention,
FIG. 9 is a diagram showing the phase relationship between the data signal and the sampling clock pulse generated by the sampling clock pulse generation circuit of the present invention, and FIG. 10a is an eye pattern diagram obtained by the conventional sampling clock pulse generation circuit. , FIG. 10b is an eye pattern diagram obtained by the sampling clock pulse generation circuit of the present invention, FIG. 11 is a diagram showing group delay characteristics when the present invention is implemented, and FIG. 12 is a diagram showing group delay characteristics. FIG. 3 is a diagram showing the relationship between the amount and the eye height rate. 2...Clock run-in signal, 3...Data signal,
7...Sampling clock pulse generation circuit, 12
...Sampling clock pulse, A...A...Character multiplex transmitter, B...Character multiplex receiver, DL...Group delay amount.

Claims (1)

[Claims] 1. A digital transmission line system with different group delays in the low and high frequency bands has a certain level period.
A device for receiving a clock run-in signal 2 in a high frequency band transmitted after T' and a data signal 13 following the clock run-in signal 2 is provided, and the data signal 13 is synchronized with the clock run-in signal 2.
In the sampling clock pulse generation circuit 7 that generates the sampling clock pulse ○H for sampling the clock run-in signal ○A, the reference frequency signal creation means 1 creates a signal ○C with a reference frequency n times higher than the clock run-in signal ○A.
6, 17, and frequency dividing means 19 for dividing the reference frequency signal ○C to create the sampling clock pulse ○H.
and rising detection reset means 15 and 18 for detecting the rising edge of the first pulse of the clock run-in signal ○a and initializing the frequency dividing means 19 using the detection signals ○ro and ○c. A sampling clock pulse generation circuit comprising: and.