JPH0159679B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit, and particularly to a sense amplifier circuit with excellent radiation resistance used in a CMOS memory circuit.

[Technical background of the invention]

Generally, a sense amplifier circuit with a CMOS configuration is
For example, it is configured as shown in FIG. That is, a current mirror circuit is provided between one end of a pair of input transistors Q ₁ and Q ₂ to which an input signal D _IN and a reference voltage V _ref are applied to their respective gates and a power supply terminal 11 to which a power supply voltage V _CC is applied. The other ends of the transistors Q ₁ and _{Q 2 are} connected in common and grounded via the transistor _{Q 5} . A predetermined potential V _R is applied to the gate of this transistor _Q5 to make it conductive, and it functions as a constant current source. A comparison output OUT between the input signal D _IN and the reference voltage V _ref is obtained from the connection point between the transistors Q ₁ and Q ₃ . Note that the back gates of transistors Q ₁ , Q ₂ and Q ₅ are grounded, and the back gates of transistors Q ₃ , Q ₄
The back gate of is connected to the power supply terminal 11.

In the above configuration, when the level of the input signal D _IN is lower than the reference voltage V _ref , the transistor
Q ₁ is in the off state, Q ₂ is in the on state and the output signal
OUT becomes high (“H”) level. On the other hand, if the level of the input signal D _IN exceeds the reference voltage V _ref ,
Transistor Q ₁ is turned on, transistor Q ₂ is turned off, and the output signal OUT becomes low (“L”) level.

[Problems with background technology]

By the way, semiconductor elements (MOS transistors)
When irradiated with radiation, the negative charges in the gate oxide film are repelled by the radiation and the gate oxide film becomes positively charged, resulting in a relative decrease in the threshold voltage of each transistor (negative (shift in the direction of ). The shift amount of this threshold voltage is MOS
It depends on the voltage between the gate and back gate of the transistor, and now, in the circuit shown in Figure 1, the level of the input signal D _IN is in the relationship "D _IN > V _ref " with respect to the reference voltage V _ref . If there is, then the threshold voltage V _TH1 of transistor Q ₁ after radiation irradiation
becomes lower than the threshold voltage V _TH2 of transistor Q ₂ . As a result, the symmetry of the sense amplifier is lost, resulting in unstable sensing operation and reduced sensitivity.

FIG. 2 shows a sense amplifier circuit for detecting the potential of a bit line BL to which the output of a memory cell is supplied.The circuit shown in FIG. 1 is arranged symmetrically to stabilize the sensing operation. In the figure, the same components as in FIG. 1 are given the same reference numerals, and their explanations will be omitted. Even in this configuration, as with the circuit shown in FIG. 1, the symmetry of the sense amplifier is lost due to radiation irradiation, resulting in unstable operation and reduced sensitivity.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to prevent radiation damage.
By equalizing the amount of shift in the threshold voltage of the MOS transistor throughout the circuit, the symmetry of the sense amplifier can be maintained even after radiation irradiation, and the sense amplifier has excellent radiation resistance, allowing stable and highly sensitive operation. The purpose of the present invention is to provide an amplifier circuit.

[Summary of the invention]

That is, in this invention, in order to maintain the symmetry of the circuit by equalizing the shift amount of the threshold voltage of the MOS transistor over the entire circuit due to radiation irradiation, the input signal or reference voltage is input from one end. A pair of first and second input MOSs of the first conductivity type and whose back gate is grounded.
A transistor is provided, and a predetermined potential generated by a potential generating means is applied to the gates of the first and second MOS transistors to set them conductive.
The structure is such that current is selectively supplied to the other ends of the two MOS transistors by potential supply means, respectively, and an output is obtained from the other ends of the first or second MOS transistors.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. That is, a pair of first and second input MOS transistors Q 6 , Q ₇ are of the first conductivity type (N-channel type), one end of which is connected to the signal input terminal 12 or the reference voltage V _ref application terminal ₁₃ , and the back gate of which is grounded. and these transistors Q ₆ ,
A predetermined potential V _R generated by a potential generating means (not shown) is applied to the gate of _Q7 to set it conductive.
Further, between the other ends of the transistors Q ₆ and Q ₇ and the power supply terminal 11 to which the power supply voltage V _CC is applied, there are provided third and fourth MOS transistors of the second conductivity type (P channel type), respectively, which serve as current supply means. Transistors Q ₈ , Q ₉
Insert and connect. The gates of the transistors Q ₈ and Q ₉ are commonly connected to the connection point between the transistors Q ₉ and Q ₇ , and the back gates are connected to the power terminal 11, respectively.
Connect to. A comparison output OUT between the input signal D _IN and the reference voltage V _ref is obtained from the connection point between the transistors Q ₆ and Q ₈ . Note that the output potential V _R of the potential generation means is higher than the threshold voltages V _TH6 and V _TH7 of the transistors Q ₆ and Q ₇ , and is lower than the power supply voltage V _CC
and the potential V _R is larger than the reference voltage V _ref , that is, the relationship is as shown in the following equations (1) and (2).

V _TH6 , V _TH7 <V _R <V _CC (1) V _ref <V _R <V _CC (2) Next, the operation in the above configuration will be explained. Now, set the potential V _D of the input signal D _IN to 0V and the reference voltage
Assume that V _ref is 1.0V, the threshold voltages V _TH6 and V _TH7 of transistors Q ₆ and Q ₇ are each 0.5 V, and the output voltage _VR of the potential generation means is 3.0 V. At this time, transistors Q ₆ and Q ₇ are on, and transistors Q ₉ and
The potential of the connection point N ₁ with Q ₇ is the potential of transistors Q ₇ , Q ₉
The conduction resistance becomes a predetermined potential (1 to 1.5 V) between the reference voltage V _ref and the power supply voltage V _CC determined by the reference voltage V _ref and the power supply voltage V _CC , and the output signal
OUT is almost the input signal potential V _D (0V) or “L”
level. On the other hand, when the input signal potential V _D exceeds the voltage obtained by subtracting the threshold voltage of the transistor Q ₆ from the voltage V _R , the transistor Q ₆ turns off, and the transistor Q ₇ remains on. Therefore,
The connection point _N1 is maintained at the predetermined potential, and the output signal is
OUT becomes the power supply voltage V _CC (“H” level).

According to such a configuration, the N-channel type
MOS transistors Q ₆ , Q ₇ and P channel type
The voltage between the gate and back gate of MOS transistors Q ₈ and Q ₉ is the same for those of the same conductivity type,
Even if the threshold voltage changes due to radiation irradiation, the symmetry of the sense amplifier will not be lost, allowing stable and highly sensitive operation.

In the above embodiment, the input signal D _IN and the reference voltage V _ref are connected to one end of the transistors Q ₆ and Q ₇ , respectively.
However, differential input signals D _IN and _IN may be supplied to one ends of these transistors Q ₆ and Q ₇ , respectively. The operation in this case is expressed as the input signal D _IN potential V _D
= 1.5V, potential of input signal _IN V _D = 2.5V, V _R =
3V, V _TH6 = V _TH7 = 0.8V. At this time, transistor Q ₆ is on, Q ₇ is off, and connection point N ₁ is at “H” level (V _CC − | V _TH9
|), increasing the conduction resistance of transistor _Q9 . As a result, the output signal OUT becomes approximately equal to the input signal voltage V _D (1.5V). On the other hand, the potential V _D
= 2.5V and V _D = 1.5V, transistor Q ₆ is turned off and Q ₇ is turned on, the connection point N ₁ becomes approximately the input signal voltage V _D (1.5V), and transistor Q ₈ becomes conductive. The resistance decreases and the output signal OUT becomes approximately at the V _CC level.

FIG. 4 shows another embodiment of the present invention, in which _{the gates of transistors Q 8 and Q 9 in FIG} . Connection point N ₂ with Q ₆
are cross-connected. In the figure, the same components as those in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted. In the above configuration, when the input signal voltage V _D is lower than the reference voltage V _ref , both transistors Q ₆ and Q ₇ are on, and the output signal OUT is at almost the same potential as the input signal voltage V _D (“ L” level). At this time, the output signal
The conduction resistance of the transistor _Q9 decreases due to the "L" level of OUT, the connection point _N1 goes to the "H" level, and the "H" level of _N1 causes the transistor Q9 to
The conduction resistance of _Q8 increases. On the other hand, the input signal voltage
When V _D is higher than the reference voltage V _ref , the transistor
Q ₆ is turned off, and transistor Q ₇ remains turned on. Therefore, the connection point N ₁ becomes V _ref and the output signal OUT becomes V _CC (“H” level).

In such a configuration, the P-channel type
MOS transistors Q ₈ and Q ₉ have different voltages applied to their gates, so these transistors Q ₈ and Q ₉
The amount of change in the threshold voltage due to radiation irradiation is different, and the sense circuit loses some symmetry, but the degree of change is smaller than in the circuit shown in FIG. This is because the bias condition for P-channel type MOS transistors Q ₈ and Q ₉ is that the gate voltage is always lower than the back gate voltage, so the shift amount of the threshold voltage due to radiation is smaller in the P-channel type than in the N-channel type. This is because the amount of change in the threshold voltages of the N-channel MOS transistors Q ₆ and Q ₇ more sensitively affects the sense sensitivity.

〔Effect of the invention〕

As explained above, according to the present invention, the shift amount of the threshold voltage of the MOS transistor due to radiation can be made uniform throughout the circuit, so the symmetry of the sense amplifier can be maintained even after radiation irradiation, resulting in stable and high sensitivity. A sense amplifier circuit with excellent radiation resistance that can perform various operations can be obtained.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining conventional sense amplifier circuits, FIG. 3 is a diagram showing a sense amplifier circuit according to one embodiment of the present invention, and FIG. 4 is a diagram showing another embodiment of the present invention. FIG. 2 is a circuit diagram for explaining an example. V _R ...First potential supply source, 12...Signal input terminal, D _IN ...Input signal, 13...Reference voltage terminal,
V _ref ... Reference voltage, Q ₆ , Q ₇ ... First and second transistors, 11... Power supply terminal, V _CC ... Power supply,
Q ₈ , Q ₉ ... 3rd, 4th transistor, OUT...
output signal.

Claims (1)

[Claims] 1: a pair of first and second input MOS transistors of a first conductivity type to which an input signal or a reference voltage is respectively supplied from one end and whose back gate is grounded;
The device includes potential generating means for applying a predetermined potential to the gates of the first and second MOS transistors to set them conductive, and current supplying means for selectively supplying current to the other ends of the first and second MOS transistors, respectively. , a sense amplifier circuit configured to obtain an output from the other end of the first or second MOS transistor. 2 The current supply means includes third and fourth MOS transistors of the second conductivity type inserted between the other ends of the pair of input first and second MOS transistors and the power supply, respectively, and the third and fourth MOS transistors of the second conductivity type The gates of the transistors are commonly connected and connected to one of the connection points of the first and third MOS transistors or the connection points of the second and fourth MOS transistors, and the back gates are respectively connected to a power supply. Sense amplifier circuit according to range 1. 3 The current supply means includes third and fourth MOS transistors of the second conductivity type which are connected between the other ends of the pair of first and second input MOS transistors and the power supply, respectively, and the gate of the third MOS transistor is connected to the connection point of the second and fourth MOS transistors, the gate of the fourth MOS transistor is connected to the connection point of the first and third MOS transistors,
2. The sense amplifier circuit according to claim 1, wherein each of the back gates is connected to a power supply.