JPH0166699U - - Google Patents

Info

Publication number
JPH0166699U
JPH0166699U JP1987161525U JP16152587U JPH0166699U JP H0166699 U JPH0166699 U JP H0166699U JP 1987161525 U JP1987161525 U JP 1987161525U JP 16152587 U JP16152587 U JP 16152587U JP H0166699 U JPH0166699 U JP H0166699U
Authority
JP
Japan
Prior art keywords
amplifier
frequency
delay
output
frequency signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987161525U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987161525U priority Critical patent/JPH0166699U/ja
Publication of JPH0166699U publication Critical patent/JPH0166699U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による周波数記憶
装置を示すブロツク図、第2図a〜iは上記実施
例装置の動作を説明するためのタイミングチヤー
ト、第3図a,bは上記実施例装置における分波
器の特性例を示すグラフ、第4,5図はいずれも
この考案の他の実施例による周波数記憶装置を示
すブロツク図、第6図は従来の周波数記憶装置を
示すブロツク図、第7図a〜eは上記従来装置の
動作を説明するためのタイミングチヤートである
。 図において、5……遅延線、8……分波器、9
……合成器、11a,11b……増幅器、12a
,12b……ループ制御スイツチ、L……遅延合
成ループ回路。なお、図中、同一の符号は同一、
又は相当部分を示している。
FIG. 1 is a block diagram showing a frequency storage device according to an embodiment of the invention, FIGS. 2 a to i are timing charts for explaining the operation of the device of the above embodiment, and FIGS. 3 a and b are diagrams of the above embodiment. A graph showing an example of the characteristics of a duplexer in the device; FIGS. 4 and 5 are block diagrams showing a frequency storage device according to another embodiment of the invention; FIG. 6 is a block diagram showing a conventional frequency storage device; FIGS. 7a to 7e are timing charts for explaining the operation of the above-mentioned conventional device. In the figure, 5...delay line, 8...brancher, 9
...Synthesizer, 11a, 11b...Amplifier, 12a
, 12b...Loop control switch, L...Delay synthesis loop circuit. In addition, in the figures, the same symbols are the same,
Or a considerable portion is shown.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力された高周波信号を増幅する増幅器と同増
幅器により増幅された信号を遅延させる遅延線と
をそなえ、上記増幅器の出力に所定の減衰と上記
遅延線による遅延とを与えて上記増幅器に入力す
る遅延合成ループ回路を構成し、同遅延合成ルー
プ回路内で上記高周波信号を循環させることによ
つて上記高周波信号の周波数を記憶する周波数記
憶装置において、上記遅延合成ループ回路に分波
器と合成器とを挿入し、上記分波器により分波さ
れた上記高周波信号の周波数ごとの各出力と上記
合成器の各入力との間に、それぞれ、上記増幅器
と同増幅器からの出力の通過をオン/オフ制御す
るループ制御スイツチとが介設されたことを特徴
とする周波数記憶装置。
A delay device comprising an amplifier for amplifying an input high frequency signal and a delay line for delaying the signal amplified by the amplifier, giving the output of the amplifier a predetermined attenuation and a delay due to the delay line, and inputting the output to the amplifier. In a frequency storage device that constitutes a synthesis loop circuit and stores the frequency of the high-frequency signal by circulating the high-frequency signal within the delay synthesis loop circuit, the delay synthesis loop circuit includes a branching filter and a synthesizer. is inserted between each output of each frequency of the high-frequency signal demultiplexed by the demultiplexer and each input of the combiner, and turns on/off the passage of the amplifier and the output from the amplifier, respectively. A frequency storage device characterized in that a loop control switch for controlling the frequency is provided.
JP1987161525U 1987-10-21 1987-10-21 Pending JPH0166699U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987161525U JPH0166699U (en) 1987-10-21 1987-10-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987161525U JPH0166699U (en) 1987-10-21 1987-10-21

Publications (1)

Publication Number Publication Date
JPH0166699U true JPH0166699U (en) 1989-04-28

Family

ID=31444537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987161525U Pending JPH0166699U (en) 1987-10-21 1987-10-21

Country Status (1)

Country Link
JP (1) JPH0166699U (en)

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