JPH0184017U - - Google Patents

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Publication number
JPH0184017U
JPH0184017U JP1987179221U JP17922187U JPH0184017U JP H0184017 U JPH0184017 U JP H0184017U JP 1987179221 U JP1987179221 U JP 1987179221U JP 17922187 U JP17922187 U JP 17922187U JP H0184017 U JPH0184017 U JP H0184017U
Authority
JP
Japan
Prior art keywords
inputs
signal
output
sine
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987179221U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987179221U priority Critical patent/JPH0184017U/ja
Publication of JPH0184017U publication Critical patent/JPH0184017U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示すシンクロ・
デイジタル変換装置を示す構成図、第2図は従来
のシンクロ・デイジタル変換装置を示す構成図、
第3図は従来のシンクロ・デイジタル変換装置の
正常・異常の判定装置を示す図である。 図において、1はスコツト・トランス、2は象
限選択回路、3は余弦乗算器、4a,4bは正弦
乗算器、5a,5bは引き算器、6はトランス、
7は位相検波器、8は電圧制御発振器、9は可逆
カウンタ、10は基準値発生器、11は比較器、
12は従来のシンクロ・デイジタル変換装置、1
3はデイジタル・シンクロ変換装置、14は切換
回路、15は比較演算回路である。なお、各図中
同一符号は同一または相当部分を示す。
Figure 1 shows an embodiment of this invention.
A block diagram showing a digital converter; FIG. 2 is a block diagram showing a conventional synchro-digital converter;
FIG. 3 is a diagram showing a conventional device for determining whether a synchro-digital converter is normal or abnormal. In the figure, 1 is a Scott transformer, 2 is a quadrant selection circuit, 3 is a cosine multiplier, 4a, 4b are sine multipliers, 5a, 5b are subtracters, 6 is a transformer,
7 is a phase detector, 8 is a voltage controlled oscillator, 9 is a reversible counter, 10 is a reference value generator, 11 is a comparator,
12 is a conventional synchro-digital converter; 1
3 is a digital synchro conversion device, 14 is a switching circuit, and 15 is a comparison circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 3相のシンクロ信号を入力し、2相のレゾルバ
信号に変換するスコツト・トランスと、上記スコ
ツト・トランスからの正弦波の信号と上記可逆カ
ウンタの出力を入力し、上記可逆カウンタの出力
データの余弦の値を正弦波の信号に掛け算する余
弦乗算器と、上記スコツト・トランスからの余弦
波の信号と上記可逆カウンタの出力を入力し、上
記可逆カウンタの出力データの正弦の値を余弦波
の信号に掛け算する第1の正弦乗算器と、上記余
弦乗算器と第1の正弦乗算器の出力信号を入力し
、それらの差を出力する第1の引き算器と、2つ
の入力端の第1の入力端に上記第1の引き算器の
出力信号を入力し、第2の入力端に搬送波を入力
し、第1の入力端の信号の搬送波を検波、整流す
る位相検波器と、上記位相検波器の出力信号を入
力し、クロツク信号を出力する電圧制御発振器と
、2つの入力端の第1の入力端に上記位相検波器
の出力信号を入力し、第2の入力端に上記電圧制
御発振器のクロツク信号を入力し、上昇または下
降のカウントをする上記可逆カウンタと、上記搬
送波と上記可逆カウンタの出力を入力し、上記可
逆カウンタの出力データの正弦の値と上記搬送波
の値を掛け算する第2の正弦乗算器と、上記第2
の正弦乗算器の出力信号と上記スコツト・トラン
スの正弦波の出力信号を入力し、それらの差を出
力する第2の引き算器と、基準値信号を発生する
基準値発生器と、上記第2の引き算器の出力と上
記基準器発生器の出力する基準値を入力し、上記
2つの入力の比較を行い、その結果を出力する比
較器とを備えたことを特徴とするシンクロ・デイ
ジタル変換装置。
A Scotto transformer inputs a 3-phase synchronized signal and converts it into a 2-phase resolver signal, and inputs a sine wave signal from the Scotto transformer and the output of the reversible counter, and calculates the cosine of the output data of the reversible counter. a cosine multiplier that multiplies the sine wave signal by the value of a first sine multiplier that multiplies the above-mentioned cosine multiplier and the first sine multiplier, a first subtracter that inputs the output signals of the cosine multiplier and the first sine multiplier and outputs the difference between them; a phase detector that inputs the output signal of the first subtracter to an input terminal, inputs a carrier wave to a second input terminal, and detects and rectifies the carrier wave of the signal at the first input terminal; and the phase detector The output signal of the phase detector is input to the first input terminal of the two input terminals, and the output signal of the voltage controlled oscillator is input to the second input terminal. a reversible counter that inputs a clock signal and counts up or down, and a second circuit that inputs the carrier wave and the output of the reversible counter and multiplies the sine value of the output data of the reversible counter by the value of the carrier wave. and the second sine multiplier
a second subtracter that inputs the output signal of the sine multiplier of the sine wave and the sine wave output signal of the Scott transformer and outputs the difference therebetween; a reference value generator that generates a reference value signal; A synchro-digital conversion device comprising: a comparator that inputs the output of the subtracter and the reference value output from the reference generator, compares the two inputs, and outputs the result. .
JP1987179221U 1987-11-25 1987-11-25 Pending JPH0184017U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987179221U JPH0184017U (en) 1987-11-25 1987-11-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987179221U JPH0184017U (en) 1987-11-25 1987-11-25

Publications (1)

Publication Number Publication Date
JPH0184017U true JPH0184017U (en) 1989-06-05

Family

ID=31470782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987179221U Pending JPH0184017U (en) 1987-11-25 1987-11-25

Country Status (1)

Country Link
JP (1) JPH0184017U (en)

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