JPH02113444U - - Google Patents
Info
- Publication number
- JPH02113444U JPH02113444U JP2133789U JP2133789U JPH02113444U JP H02113444 U JPH02113444 U JP H02113444U JP 2133789 U JP2133789 U JP 2133789U JP 2133789 U JP2133789 U JP 2133789U JP H02113444 U JPH02113444 U JP H02113444U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- data
- digital data
- analog
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の実施例を示すブロツク図、
第２図は第１図に示すブロツク図の各箇所に流れ
る信号のタイム・チヤートである。
１１……Ｄ／Ａ変換器、１４……加算器、１５
……減衰器、１８……切換回路、ＤＡ０〜ＤＡ７
……Ｄ／Ａ変換回路。
Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a time chart of signals flowing through various parts of the block diagram shown in FIG. 11...D/A converter, 14...Adder, 15
...Attenuator, 18...Switching circuit, DA0 to DA7
...D/A conversion circuit.
Claims (1)
それに対応する値のアナログ信号に変換する少な
くとも２台のデイジタル／アナログ変換回路、 上記所定ビツト数よりも多いビツト数の元デイ
ジタル・データを上記所定ビツト数以下の少なく
とも２つのデイジタル・データに所定の分割比で
分割して上記デイジタル／アナログ変換回路にそ
れぞれ与えるデータ出力手段、および 上記デイジタル／アナログ変換回路から出力さ
れるアナログ信号を上記分割比で加算する加算回
路、 を備えたデイジタル／アナログ変換装置。 (2) 上記デイジタル／アナログ変換回路は入力
デイジタル・データに対応する出力アナログ信号
を次の入力デイジタル・データが与えられるまで
保持するものであり、上記データ出力手段は上記
の少なくとも２つのデイジタル／アナログ変換回
路に、少なくとも２つに分割されたデイジタル・
データを時分割で与える請求項(1)に記載のデイ
ジタル／アナログ変換装置。 (3) 上記データ出力手段は複数個の元デイジタ
ル・データを時分割で出力するものであり、 上記加算回路の出力を時分割で出力される元デ
イジタル・データごとに切換える切換回路と、 切換回路の各出力信号を次の切換時点までそれ
ぞれ保持する複数個の保持回路とを、 さらに備えている、請求項(2)に記載のデイジ
タル／アナログ変換装置。[Claims for Utility Model Registration] (1) At least two digital/analog conversion circuits for converting input digital data of a predetermined number of bits into an analog signal of a value corresponding thereto; data output means that divides the original digital data into at least two pieces of digital data each having a predetermined number of bits or less at a predetermined division ratio and supplies the divided data to the digital/analog conversion circuit, and the digital data output from the digital/analog conversion circuit; A digital/analog conversion device comprising: an addition circuit that adds analog signals at the above division ratio; (2) The digital/analog conversion circuit holds the output analog signal corresponding to the input digital data until the next input digital data is given, and the data output means is configured to hold the output analog signal corresponding to the input digital data. The conversion circuit has at least two digital
The digital/analog conversion device according to claim 1, wherein the data is provided in a time-division manner. (3) The data output means outputs a plurality of original digital data in a time-division manner, and includes a switching circuit that switches the output of the adder circuit for each original digital data output in a time-division manner, and a switching circuit. The digital/analog converter according to claim 2, further comprising: a plurality of holding circuits that hold each output signal until the next switching point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133789U JPH02113444U (en) | 1989-02-28 | 1989-02-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133789U JPH02113444U (en) | 1989-02-28 | 1989-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02113444U true JPH02113444U (en) | 1990-09-11 |
Family
ID=31238489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2133789U Pending JPH02113444U (en) | 1989-02-28 | 1989-02-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02113444U (en) |
-
1989
- 1989-02-28 JP JP2133789U patent/JPH02113444U/ja active Pending
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