JPH02116341U - - Google Patents
Info
- Publication number
- JPH02116341U JPH02116341U JP2280989U JP2280989U JPH02116341U JP H02116341 U JPH02116341 U JP H02116341U JP 2280989 U JP2280989 U JP 2280989U JP 2280989 U JP2280989 U JP 2280989U JP H02116341 U JPH02116341 U JP H02116341U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- switching
- control
- control cpu
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005856 abnormality Effects 0.000 claims description 5
- 239000013256 coordination polymer Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
Landscapes
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Description
第１図は本考案による第１の実施例を示す概略
ブロツク構成図、第２図は第１の実施例において
バス切替制御部がＣＰＵ異常警報を受信した場合
の処理動作を説明する為のブロツク図、第３図は
第１図と第２図を含む本考案による第１の実施例
の全体を示す具体的ブロツク構成図、第４図は本
考案による第２の実施例を示すブロツク構成図で
ある。
１……制御ＣＰＵ、２……制御ＣＰＵ１のバス
、３……共有バス切替回路、４……共有バス、５
……制御対象、６……制御ＣＰＵ、７……制御Ｃ
ＰＵ６のバス、８……バス切替要求信号、９……
バス切替承認信号、１０……バス切替制御部、１
１……バス切替部、１２，１３……ＣＰＵ異常検
出回路、１４……制御ＣＰＵ１バス切り放し命令
信号、１５……制御ＣＰＵ６バス切り放し命令信
号、１６……制御ＣＰＵ１異常警報、１７……制
御ＣＰＵ６異常警報、１８……反転論理回路、１
９……論理和回路、２０，２１……論理積回路、
２２……制御ＣＰＵ１からのクロツク、２３……
制御ＣＰＵ６からのクロツク、２４，２５……ク
ロツク断検出回路、２６……制御ＣＰＵ１からの
クロツクの断警報、２７……制御ＣＰＵ６からの
クロツクの断警報、２８……反転論理回路。
FIG. 1 is a schematic block configuration diagram showing a first embodiment of the present invention, and FIG. 2 is a block diagram for explaining processing operations when the bus switching control section receives a CPU abnormality alarm in the first embodiment. 3 is a concrete block configuration diagram showing the entire first embodiment according to the present invention including FIGS. 1 and 2, and FIG. 4 is a block diagram showing the second embodiment according to the present invention. It is. 1... Control CPU, 2... Bus of control CPU 1, 3... Shared bus switching circuit, 4... Shared bus, 5
... Controlled object, 6 ... Control CPU, 7 ... Control C
Bus of PU6, 8... Bus switching request signal, 9...
Bus switching approval signal, 10...Bus switching control unit, 1
1... Bus switching unit, 12, 13... CPU abnormality detection circuit, 14... Control CPU1 bus disconnection command signal, 15... Control CPU6 bus disconnection command signal, 16... Control CPU1 abnormality alarm, 17... Control CPU6 Abnormal alarm, 18...Inversion logic circuit, 1
9...OR circuit, 20, 21...AND circuit,
22...Clock from control CPU1, 23...
Clock from the control CPU 6, 24, 25...Clock break detection circuit, 26...Clock break alarm from the control CPU 1, 27...Clock break alarm from the control CPU 6, 28...Inverted logic circuit.
Claims (1)
御ＣＰＵの共通の制御対象への共有バスに接続す
る共有バス切替回路において、一方の制御ＣＰＵ
からのバスの切替要求信号を受信して他方のＣＰ
Ｕに送信する手段と、前記バス切替要求信号を受
信した制御ＣＰＵからのバスの切替承認信号を受
信して前記切替を要求した制御ＣＰＵへ返送する
手段と、前記切替要求信号と切替承認信号により
バスを切り替える手段と、前記各制御ＣＰＵから
の異常警報信号により正常な制御ＣＰＵ側のバス
を共有バスに接続する手段と、バスの切替に伴つ
て前記各制御ＣＰＵから制御対象へ送出している
クロツクを切り替える手段と、前記クロツクの断
検出を行う手段と、クロツク断を検出すると異常
を両制御ＣＰＵに通知する手段と、クロツク断を
表わす警報信号により正常にクロツクを送つてい
る制御ＣＰＵのバスを共有バスに接続する手段と
、バス使用権（切替要求、承認信号）を正常な制
御ＣＰＵ側に渡すと手段を有することを特徴とし
た共有バス切替回路。 In a shared bus switching circuit that switches buses from two control CPUs and connects them to a shared bus to a common control target of the control CPUs, one of the control CPUs
The other CP receives a bus switching request signal from the other CP.
means for receiving a bus switching approval signal from a control CPU that has received the bus switching request signal and sending it back to the control CPU that requested the switching; means for switching buses; means for connecting a bus on a normal control CPU side to a shared bus in response to an abnormality alarm signal from each of the control CPUs; means for switching the clock, means for detecting the clock disconnection, means for notifying both control CPUs of an abnormality when the clock disconnection is detected, and a bus for the control CPU that normally sends the clock by an alarm signal indicating the clock disconnection. 1. A shared bus switching circuit comprising means for connecting a bus to a shared bus, and means for passing a bus usage right (switching request, approval signal) to a normal control CPU side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2280989U JPH0716187Y2 (en) | 1989-02-28 | 1989-02-28 | Shared bus switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2280989U JPH0716187Y2 (en) | 1989-02-28 | 1989-02-28 | Shared bus switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02116341U true JPH02116341U (en) | 1990-09-18 |
| JPH0716187Y2 JPH0716187Y2 (en) | 1995-04-12 |
Family
ID=31241253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2280989U Expired - Lifetime JPH0716187Y2 (en) | 1989-02-28 | 1989-02-28 | Shared bus switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0716187Y2 (en) |
-
1989
- 1989-02-28 JP JP2280989U patent/JPH0716187Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0716187Y2 (en) | 1995-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB2290891B (en) | Multiprocessor system | |
| JPH02116341U (en) | ||
| JPH0726762Y2 (en) | Bus mismatch circuit | |
| JPS6356755A (en) | Abnormality supervising system for slave processor | |
| JPH0755179Y2 (en) | Parallel multiple electronic interlocking device | |
| JPH01166161A (en) | Mutual monitoring system for multiprocessor system | |
| JPH046030B2 (en) | ||
| JPH04123145A (en) | Microcomputer | |
| JPH03204761A (en) | Bus connecting device | |
| JPS6031334A (en) | Fault supervisory system of communication system | |
| JPH0795282B2 (en) | Duplex microprocessor automatic switching device | |
| JP2592676B2 (en) | System switching method | |
| JP2003067216A (en) | CPU redundant system | |
| JPS60254338A (en) | Abnormality detecting system of multiprocessor | |
| JPH03115345U (en) | ||
| JPS6089255A (en) | Trouble informing system in decentralized processing type bus system | |
| JPS6225795Y2 (en) | ||
| JPH10232825A (en) | Cache memory control system | |
| JPH01151641U (en) | ||
| JPH0535460B2 (en) | ||
| JPS6326065B2 (en) | ||
| JPH0342750A (en) | Bus occupation supervisory system | |
| JPS58114141A (en) | Fault reporting system for multimicroprocessor | |
| JPH044340U (en) | ||
| KR960008567A (en) | How to claim common bus occupancy rights on multiple processors |