JPH02125547A - Loop network system - Google Patents

Abstract

PURPOSE:To prevent the selection of an ineffective insert signal in a slave node by providing a slave node converting an inputted transmission data into an insert signal, inserting the insert signal to a frame received from a transmission line when the insert signal is effective and outputting the result to the transmission line. CONSTITUTION:A transmission data (e), and a transmission clock (f) from an insert timing generating circuit 31 are inputted to a transmission interface circuit 50, the transmission data (e) is converted into an insert signal (g) and outputted to a selection circuit 32. Simultaneously, the transmission interface circuit 50 outputs an insert request signal (j) representing effective/ineffective state of the insert signal (g) to other input terminal of an AND gate 33. When the insert signal (g) inputted to the selection circuit 32 is ineffective, the AND gate 33 is turned off with the insert request signal (j) representing the ineffective state. Thus, an output signal (i) from the insert timing generating circuit 31 is not outputted to the selection circuit 32, and the transmission frame (h) outputted from the selection circuit 32 is a signal for a reception frame (a).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a loop network system used in the information and communication field.

[Conventional technology]

This type of loop network system includes a drop insert type loop network system that includes a master node and slave nodes. In this drop-insert type loop network system, one master node and a plurality of slave nodes are connected in a loop.

The mask node has a frame generation function and a frame delay correction function, and the slave node has a frame drop function and a frame insert function.

An example of this slave node is shown in FIG. This slave node includes a synchronization detection circuit 60 for received frame a, a drop circuit 70 for received frame a, and a drop circuit 70 for received frame a.
A reception interface circuit 90 receives a drop signal S and a reception clock C from the input terminal, converts the drop signal S into reception data d, and converts the transmission data e into an insert signal g.
a transmission interface circuit 100 that converts the insert signal g into the received frame a; a selection circuit 82 that inserts the insert signal g into the received frame a;
The insert timing generation circuit 81 outputs a transmission clock f to the transmission interface circuit 100 and outputs an output signal i to the selection circuit 82. Further, the insert section 80 includes an insert timing generation circuit 81 and a selection circuit 82.

Based on the output signal i from the insert timing generation circuit 81, such a slave node inserts the insert signal g into the received frame a, thereby creating the transmitted frame h. That is, the insert timing generation circuit 81
The output signal i is used as the selection input of the selection circuit 820.

[Problem to be solved by the invention]

In the conventional loop network system described above, the output signal of the insert timing generation circuit is used as the selection input of the selection circuit in the slave node, so when the transmission interface circuit is out of order or removed, There is a drawback that an invalid insert signal is selectively output by the selection circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a loop network system that can eliminate such drawbacks and prevent selection of invalid insert signals at slave nodes.

[Failure to solve the problem]

The present invention provides a loop network system that includes a master node that generates frames and outputs them to a transmission path, which converts input transmission data into an insert signal, and when this insert signal is valid, inserts data into a frame received from the transmission path. It is characterized in that it has a slave node that inserts this insert signal and outputs it to a transmission line, and the master node and the plurality of slave nodes are connected in a loop via the transmission line.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an overall configuration diagram showing one embodiment of the present invention.

This loop network system is composed of one master node 1 and four slave nodes 2.

In the loop network system having such a configuration, the master node 1 has a frame generation function and a loop delay correction function. The master node 1 and the four slave nodes 2 are connected in a loop via a transmission line 3.

The slave node 2 receives the frame from the transmission path 3, converts it into a drop signal, further converts this drop signal, and outputs received data. Also, slave node 2
converts the input transmission data to an insert signal,
This insert signal is sent to transmission line 3 at the insert timing.
Send to.

Furthermore, the slave node 2 can be prevented from transmitting an invalid insert signal to the transmission path 3. An example of such a slave node is shown in FIG.

The slave node shown in FIG.
, a drop circuit 20 , an insert section 30 , a reception interface circuit 40 , and a transmission interface circuit 50
It is made up of. Furthermore, the insert section 30 includes an insert timing generation circuit 31, a selection circuit 32,
AND gate 33.

In the slave node with such a configuration, the synchronization detection circuit 10 is connected to the F/Soviet 1 circuit 20 and the insert timing generation circuit 31 of the inserter 1 part 30, and is connected to the transmission line 3.
The input signal is received frame a from .

The drop circuit 20 uses the output signal output from the synchronization detection circuit 10 as a timing trigger.

Then, the reception clock C and the drop signal S obtained by converting the reception frame a are outputted to the reception interface circuit 40.

The reception interface circuit 40 converts the drop signal from the drop circuit 20 and outputs reception data d.

The transmission interface circuit 50 inputs the received data e and the transmission clock f from the insert timing generation circuit 31, converts the received data e, and generates an insert signal g.
is output to the selection circuit 32. At the same time, the transmission interface circuit 50 outputs an insert request signal j indicating whether the insert signal g is valid or invalid to the AND gate 33.

Insert timing generation circuit 31 of insert section 30
uses the output signal from the synchronization detection circuit 10 as a timing trigger. Furthermore, the insert timing of the insert signal g is set in advance in the insert timing generation circuit 31. Then, the insert timing generation circuit 31 outputs an output signal i related to this insert timing.

The AND gate 33 receives the output signal i from the insert timing generation circuit 31, which is input to one input terminal, and
A logical product is performed with the insert request signal j from the transmission interface circuit 50, which is input to the other input terminal. This determines whether the output signal i is output to the selection circuit 32 or not. That is, when the insert signal g input to the selection circuit 32 is valid, the insert request signal j indicates which insert toy No. 3 is valid. This insert request signal j turns the AND gate 33 into the "on" state, and output signal i is output to the selection circuit 32. Further, when the insert signal g is invalid, the insert request signal j indicates that the insert signal g is invalid. This insert request signal j turns the AND gate 33 into an "off" state, and the output signal i is not output.

When the output signal i is input to the selection input terminal S, the selection circuit 32 selects the insert signal g input to the input terminal B.
It is output as a transmission frame h from output terminal Y at the insert timing indicated by output signal i. Further, when the output signal i is not input, the selection circuit 32 outputs the reception frame a input to the input terminal Δ as a signal of the transmission frame h.

Next, the operation of this embodiment will be explained.

A frame is generated at the master node 1 and transmitted to the transmission path 3. Slave node 2 receives this frame from transmission path 3. As shown in FIG. 2, in the slave node 2, the received frame a is sent to the synchronization detection circuit 10.
is input to the drop circuit 20 and the insert section 30. The drop circuit 20 uses the signal output from the synchronization detection circuit 10 as a timing trigger, and converts the received clock C and the drop signal S obtained by converting the received frame a.
It is output to the receiving interface circuit 40. A reception interface circuit 40 converts this drop signal d and outputs reception data d.

On the other hand, the transmission interface circuit 50 receives the transmission data e.
and a transmission clock f from the insert timing generation circuit 3I. The transmitting ink face circuit 50
The transmission data e is converted into an insert signal g and outputted to the selection circuit 32. At the same time, the transmission interface circuit 50
outputs an insert request signal j indicating whether the insert signal g is valid or invalid to the other input terminal of the AND gate 33. Further, the insert timing generation circuit 31 outputs an output signal i related to the insert timing of the insert signal g to one input terminal of the AND gate 33.

As described above, the received frame a input to the insert section 30 is input to the input terminal A of the selection circuit 32.

The insert signal g is input to the input terminal B of the selection circuit 32. When this insert signal g is valid, the insert request signal j indicates that the insert signal g is valid. When this insert request signal j is input to the other input terminal of the AND gate 33, the AND gate 33 enters the "on" state.

That is, the output signal i from the insert timing generation circuit 31 passes through the AND gate 33. Then, the output signal i is input to the selection input terminal S of the selection circuit 32.

The selection circuit 32 outputs the insert signal g input to the input terminal B to the transmission line 3 from the output terminal Y as a transmission frame h based on the insert timing of the input output signal i.

Furthermore, when the insert signal g input to the selection circuit 32 is invalid, the AND gate 33 is turned off by the insert request signal j indicating invalidity.

As a result, the output signal i from the insert timing generation circuit 31 is not output to the selection circuit 32, and the transmission frame h output from the selection circuit 32 becomes the signal of the reception frame a. This frame a is output to the transmission line 3.

In this way, the transmission frame becomes an insert signal only at the timing preset in the insert timing generation circuit and when the insert signal from the transmission interface circuit is valid, that is, the insert request signal from the transmission interface circuit is valid. , otherwise, it becomes a received frame signal. In other words, when the insert signal from the transmission interface circuit is invalid, that is, when the insert request signal from the transmission interface circuit indicates invalidity, the transmission frame becomes the reception frame signal even at the insert timing, and is output from the slave node. Ru.

In addition, in the loop network system according to this embodiment, when performing 1:N or NUN communication, it is possible to prevent a malfunctioning slave node from inserting an invalid insert signal.

〔Effect of the invention〕

As explained above, the present invention enables a slave node to output a received frame signal without selectively outputting an invalid insert signal, for example, when the transmission interface circuit is out of order or when the transmission interface circuit is removed. There is an effect that can be used as an output.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is an overall configuration diagram showing an embodiment of the present invention, and Fig. 2 is a pro-7 diagram showing an example of a slave node used in the embodiment of Fig. 1. FIG. 3 is a block diagram showing an example of a slave node used in a conventional loop network system. 1...Master node 2...Slave node 3...Transmission line 10...Same p, +1 detection circuit 20...Drop circuit 30... Insert section 31... Insert timing generation circuit 32...
... Selection circuit 33 ... AND gate 40 ... Reception interface circuit 50 ...
Transmission interface circuit Figure 30 Insert sound p And gate diagram

Claims (1)

[Claims] (1) In a loop network system equipped with a master node that generates frames and outputs them to the transmission path, input transmission data is converted into an insert signal, and when this insert signal is valid, this signal is added to the frame received from the transmission path. 1. A loop network system comprising a slave node that inserts an insert signal and outputs it to a transmission path, the master node and a plurality of slave nodes being connected in a loop via the transmission path.