JPH02132548A - Debugging support method for parallel processors - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to parallel processors, and particularly to support for debugging parallel processors suitable for supporting debugging of programs.

[Conventional technology]

Conventionally, a parallel processor configured by a data transfer path that allows data transfer between a plurality of processors and an arbitrary processor is disclosed, for example, in Japanese Patent Application Laid-open No. 182361/1983.

Inter-processor data transfer processing in this parallel processor is as follows.

In the processor on the data sending side, a data sending device within the processor sends out the destination processor number, data identifier, and transfer data to the data transfer path.

On the other hand, the processor on the data receiving side holds the data identifier and the transferred data sent from the data transfer in an associative memory. At this time, a valid bit is set to 1, indicating that the content of the storage location on the associative memory is valid (that is, indicating that the transferred data has arrived).

If an instruction to be executed in the processor on the data receiving side requires the transferred data, the corresponding valid bit is set to 1 from the associative memory using the data identifier specified in the instruction. The transfer data is read after confirming that the transfer data is correct.

[Problem a that the invention seeks to solve]

In the conventional technology described above, when transfer data is required for calculation, the transfer data is read after confirming that the transfer data has arrived. However, when transfer data arrives from the data transfer path, it is not confirmed that the contents of the memory location in the corresponding associative memory is invalid (or that it has already been used within the processor), and the content of the corresponding associative memory is It is designed to be written to.

This means that, for example, if two different data transfers accidentally have the same data identifier, or
If the data identifiers are intentionally set to be the same, but the synchronization between processors is not well established, the transferred data may be overwritten in the processor on the data receiving side, and that processor may not be able to match the number of data to be received. It disappears. the result,
The processor will continue to wait for data to be received, and the execution of the entire program of the parallel processors will never end.

Conventional technology does not take the above points into consideration, making it difficult for programmers to fully understand the reason why a parallel processor's program execution does not end or where transfer data has been overwritten, resulting in poor program debugging efficiency for parallel processors. The problem was that it was getting worse.

An object of the present invention is to provide parallel processor debugging support that reports to a programmer whether or not transferred data has been overwritten and improves the efficiency of parallel processor program debugging.

[Means to solve the problem]

The above purpose is to remember when transferred data has been overwritten, and to notify the programmer of the problem after program execution has finished (for example, due to programmer intervention, interruption due to processor usage time being exceeded, etc.). This is achieved by reporting. Therefore, when a data identifier and transfer data arrive from a data transfer path, means 1 for checking whether the contents of a memory location in an associative memory are invalid based on the data identifier; As a result, if the transfer data is not invalid, means 2 is provided for reading out the transfer data held in the associative memory and temporarily storing the data identifier corresponding thereto.

[Effect]

When a data identifier and transfer data are received from the data transfer path, first, means 1 checks whether the content of the content addressable memory corresponding to the data identifier is invalid or not based on the data identifier. If the data is invalid, the transferred data is written into the associative memory, and the valid bit is set to 1, indicating that the contents of the associative memory are valid. If it is not invalid (ie, the valid bit is 1), the transfer data held in the associative memory is read and stored in the means 2 together with the data identifier corresponding thereto. Further, after the transfer data received from the data transfer path is written by the means 2, the same processing as in the case of invalidity is performed.

The program on the parallel processors is executed while data is transferred between the processors as shown above. Then, when the execution of the program of the parallel processors is completed, the processor in which the transferred data has been overwritten reports to the control processor that the overwriting has occurred. The control processor that receives the above report reads the contents of the means 2 held in the processor and notifies the programmer.

This allows the programmer to be notified of the occurrence of overwriting of transferred data, thereby improving the efficiency of program debugging for parallel processors.

C Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a parallel processor.

A data transfer path 101 is capable of transferring data between arbitrary processors, and has a function of sending data to a target processor using a receiving processor number 103 of a data packet 102. Here, the data packet 102 includes a processor number (PE#) 103 . It consists of a transfer data identifier (Key) 1 0 4 and transfer data (Data) 1 0 5. This data transfer path 101 can have various configurations such as a cross-path switch, a multi-stage switch network, and a bus. 106 is a control processor, which transfers data between the plurality of processors 110 to 111, gives execution start instructions,
It performs various controls such as execution stop instructions.

Further, although only two processors 110 to 111 are shown here, the number may be two or more in the present invention. Each of the processors 110 to 111 includes a data receiving device 120, a data transmitting device 130, and an instruction processor 140.
, and local. It consists of 150 memories.

The instruction processor 140 reads instructions from the local storage 150, decodes and executes them. The data transmitter 130 generates a data packet 102 and sends it to the data transfer path 101. Data receiving device 12
0 inputs the data packet 102 sent from the data transfer path 101 and stores its data identifier 104 and transfer data 105.

Next, a method for supporting debugging of a parallel processor will be described using FIG. Although the data transfer method described here is disclosed in Japanese Patent Laid-Open No. 182361/1982, the present invention is not particularly limited to this method.

First, in data transmission processing in the data transmission side processor, the instruction processor 140 decodes the data transmission instruction,
This is done by activating the data transmitting device 130. The data transmitting device 130 generates a data packet 102 according to the activation instruction and transmits it to the data transfer path 101.5 At this time, the data transmitting device R130 and the command processor 140 operate asynchronously, and the command processor 140 transmits the data. By simply activating the device 130, the processing necessary for data transfer is left to the data transmitting device 130. Next, data reception processing in the processor on the data reception side will be described. The data packet 102 sent from the processor on the data sending side is transferred to the data transfer path 101.
is sent to the destination processor.

In the processor on the data receiving side, when a data packet 102 arrives from the data transfer path 101, it is held in the input register 121 by the network 1-work interface control 122. Then, using the data identifier (Key) held in the input register 121, the corresponding associative memory 1
Valid bit (V) indicating whether the contents of 24 are invalid or not.
is read from the associative memory 124. The read valid bit is sent to the content addressable memory overwrite control 126 using the signal line 150.

The associative memory overwrite control 126 has a valid bit (V) of 1.
(In other words, the transfer data is held in the associative memory 124 and has not been read out from the instruction processor 140 yet), the transfer data (Data) being simultaneously read out from the associative memory 124 and its data identifier (K ey
) is written to the overwrite buffer 127. On the other hand, when the valid bit (V) indicates 0 (that is, no transfer data is held in the associative memory 124), the associative memory overwrite control 126
does nothing. Further, the valid bit (V) read from the associative memory 124 using the data identifier (Key) is also sent to the associative memory access control 123 .

In the associative memory access control 123, when the valid bit (V) is 1, after writing to the overwrite buffer 127,
As soon as the valid bit (V) is 0, the input register 12
The transfer data held at 1 is written to the content addressable memory 124.

At the same time, the valid bit (V) of the associative memory 124
Set to 1.

On the other hand, when the instruction processor 140 requires transfer data, the instruction processor 140 sends a data identifier (Key) to the reception control 125 using the signal line 151. The reception control 125 uses the associative memory 12 based on the data identifier.
The transfer data (Data) held at 4 and its valid bit (V) are read out.

When the read valid bit (V) indicates 1, the transfer data is transferred to the instruction processor 1 using the signal line 152.
Pass it to 40. At the same time, using the signal line 153, the content addressable memory access control 123 is requested to set the valid bit of the read content addressable memory 124 to O. On the other hand, when the read valid bit (V) indicates O, it waits until the corresponding transfer data arrives from the data transfer path 101.

The program on the parallel processors is executed while data is transferred between the processors as shown above. After the execution of the program is completed (for example, interruption due to programmer intervention, interruption due to overtime of processor usage, normal termination, etc.), each processor 110 to 1
11, if the associative memory has been overwritten, it is reported to the control processor 106.

As a means of reporting to the control processor 106, the instruction processor 140 indicates whether an overwrite has occurred on a signal line 154.
Various methods are conceivable, such as determining whether the error has occurred and, if it has occurred, transmitting it to the control processor 106 using interrupt means of known technology.

In addition, when the control processor 106 receives the above report, the overwrite buffer 127 of each processor 110 to 111 is
is read out via the instruction processor 140.

FIG. 2 shows an example in which a means is provided to immediately report the data identifier and the transferred data to the control processor without temporarily storing them when the transferred data is overwritten in the embodiment shown in FIG. 1. It is.

Data transmission processing in the processor on the data transmission side performs the operation explained in FIG.

In the processor on the data receiving side, when a data packet 102 arrives from the data transfer path 101, the valid bit (V) is read from the associative memory 124 as explained in FIG. control 201.

When the valid bit indicates 1, the associative memory overwrite control 201 takes in the transfer data (Data) and its data identifier (Key) that are simultaneously read from the associative memory 124, and sends the data to the instruction processor 140 using the signal line 202. Notify that an overwrite has occurred.

The instruction processor 140 that has received the report receives the data identifier (Key) and transfer data (Data) from the associative memory overwrite control 201 via the signal line 203, and reports the results to the control processor.

On the other hand, when the valid bit indicates 0 in the associative memory overwrite control 201, the operation explained in FIG. 1 is performed. Further, when the instruction processor 140 requires transfer data, the operation is the same as that shown in FIG. 1.

Further, the processors 110 to 111 that have made the above report continue to execute the program. On the other hand, whether or not to interrupt the execution of the program is under the control of the control processor 10G that has received the report.

FIG. 3 shows that the transfer data in the embodiment of FIG. 1 is not temporarily stored, but overwrite transfer data is written to the associative memory until the transfer data to be overwritten on the associative memory is read by the instruction processor. This is an example in which a temporary restraining means is provided.

First, data transmission processing in the processor on the data transmission side performs the operation described in FIG.

Next, in the processor on the data receiving side, data transfer path 1
When the data packet 102 arrives from 01, the valid bit (V) is read from the associative memory 124 as explained in FIG.
Sent to 1.

In the associative memory overwrite control 301, when the valid bit indicates 1, the contents of the input register 121 are held for the network interface control 304, and the subsequent reception of data packets 102 from the data transfer path 101 is suppressed. Set the signal line 302 to 1. When the signal line 302 becomes 1, the network interface control 304 uses the signal line 303 to notify the data transfer path 101 that no more data packets 102 can be accepted.

At the same time, the associative memory access control 305 prevents the transfer data held in the input register 121 from being written to the associative memory 124 when the valid bit is 1.

As described above, writing of overwrite transfer data to the associative memory is temporarily inhibited.

On the other hand, the method for canceling the inhibition is that the network interface control 304 controls the data transfer path 101 at a certain timing (for example, after the transfer data is read from the command processor 140), as explained in FIG. It is sufficient to operate as if the data packet 102 had been received.

The difference is that when the valid bit 150 read from the content addressable memory 124 is 0, the content addressable memory overwrite control 301 sets the signal [302 to O, and the network interface control 304 sets the data packet 10 by the signal line 303.
2 can now be accepted on data transfer path 10.
Notify 1.

If the read valid bit 150 is still 1, the state shown above (i.e., the sequence of overwrite transfer data M
Write to E memory is inhibited) and wait again for the next timing.

On the other hand, if the instruction processor 140 requires transfer data, it performs the operation described in FIG. 1.

Further, in one embodiment of the present invention, associative memory is used as a means for retaining transferred data during data transfer between processors, but there is no need to be limited to this. For example, local storage may be used to hold programs and data executed within each processor. in this case,
Each processor generates a local storage address from the data identifier received from the transfer path. Then, when storing the transfer data based on this, it can be realized by checking the valid bit indicating whether or not the transfer data has arrived, as in the embodiment of the present invention.

As described above, according to the present invention, it is possible to report to the programmer whether or not transferred data has been overwritten during data transfer between processors.

〔Effect of the invention〕

According to the present invention, in a parallel processor that can transfer data between processors, it is possible to notify a programmer that overwriting of transferred data has occurred, so that the efficiency of program debugging of the parallel processor can be improved.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention that is provided with means for storing transfer data and data identifiers to be overwritten, and FIG. 2 is an embodiment of the present invention that is provided with means for immediately reporting to a control processor when transfer data has been overwritten. One embodiment of the invention, FIG. 3 shows an embodiment of the invention in which means is provided for temporarily inhibiting writing of overwrite transfer data to the associative memory until the transfer data held in the associative memory is read by the instruction processor. This is an example. 101... Data transfer path, 110-111... Processor, 106... Control processor, 120... Data receiving device, 124... Content addressable memory, 126... Content addressable memory overwrite control, 127...・Overwrite buffer, 13
0...Data transmission device, 140...Instruction processor.

Claims (1)

[Claims] 1. In a parallel processor comprising a plurality of processors, a control processor for controlling each processor, and a communication path for data transfer between each processor, the communication path is means for checking whether the storage location of the transfer data is valid or invalid when the transfer data is received from the storage device; and when the result of the check indicates that the storage location of the transfer data is valid, notifying the control processor of the same; A debugging support method for a parallel processor characterized by providing a means. 2. A patent characterized in that, when the storage location of the transferred data is found to be valid as a result of the checking means, means is provided for storing the transferred data held in the storage location and information indicating the storage location thereof. A debugging support method for a parallel processor according to claim 1. 3. Each processor is provided with associative memory means for receiving transfer data and an identifier for the transfer data from the communication path and storing the transfer data and the identifier in the storage location. Parallel processor debugging support method described in . 4. A patent characterized in that each processor receives transferred data and an identifier for the transferred data from the communication path, and the storage location is provided with a local storage means that is accessed by a local storage address generated from the identifier. A debugging support method for a parallel processor according to claim 1. 5. In a parallel processor that includes a plurality of processors, a control processor that controls each processor, and a communication path for transferring data between each processor, each processor receives transfer data from the communication path. a means for checking whether the storage location of the transfer data is valid or invalid; and when the result of the means indicates that the storage location of the transfer data is valid, the transfer data held in the storage location is stored in the processor; Debugging support for a parallel processor, characterized in that means is provided for not writing transfer data received from the communication path to the storage location and not receiving transfer data from the transfer path until it is retrieved by various arithmetic processes. method. 6. Each processor is provided with associative memory means for receiving transfer data and an identifier for the transfer data from the communication path and storing the transfer data and the identifier in the storage location. Parallel processor debugging support method described in . 7. A patent characterized in that each processor receives transferred data and an identifier for the transferred data from the communication path, and the storage location is provided with a local storage means that is accessed by a local storage address generated from the identifier. A debugging support method for a parallel processor according to claim 3.