JPH02136062A - Gate circuit of gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To improve cut-off capacity of a GTO by bringing OFF source voltage higher than the breakdown voltage of gate and producing OFF current with voltage higher than the breakdown voltage during accumulation time then applying capacitor voltage onto the gate after accumulation time thereby increasing dig/dt. CONSTITUTION:When a monostable operation circuit 12 produces an output at time (t1) based on a command fed from a logic section 2 and a switch 6 is turned ON under ON state of a GTO3, gate current (ig) flows through a capacitor 11, the switch 6 and the cathode and gate of the GTO3 to bring out a state where gate current flows easily because the OFF source 10 voltage is higher than the breakdown voltage of the gate thus providing a high dig/dt. Upon elapse of time T, output from the monostable operating circuit 12 disappears at time (t3) and the switch 6 is turned OFF. When the source 10 voltage is E and the resistances of resistors 13-15 are R1, R2, R3, a weak reverse voltage E.R1/(R1+R2+R3) is applied and the OFF state is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a gate circuit for a gate turn-off thyristor (hereinafter referred to as G'rO), and particularly relates to an OFF gate circuit.

13. Summary of the Invention The present invention makes the OFF power supply voltage higher than the breakdown voltage of the gate in the gate circuit of the GTO, and turns off the Ti at a voltage higher than the breakdown voltage during the storage time.
By generating a current and applying a capacitor voltage to the gate during the tail time after the accumulation time, dig/dt is increased and the cutoff ability of the GTO is improved.

C1 Prior Art FIG. 4 shows a conventional gate circuit, in which an ON gate current generating circuit 1 generates a gate current based on a signal from the logic section 2 to turn on the GTO 3. 4 is a power supply for turning off, and 5 is a capacitor for generating a gate current for turning off, which is connected in parallel with the power supply 4, and when the switch 6 is turned on by the signal from the logic section 2, the GTO3
A current is passed through the cathode and gate routes to turn off the on-state GTO3.

Problems to be Solved by the Invention In order to turn off the GTO, it is necessary to quickly draw out excess minority carriers accumulated within the device. Therefore, as an OFF gate circuit, a steep (dig)
/dt) It is important to generate a pulse. but,
Since the reverse withstand voltage between the gate and cathode of GTO3 is limited by GTO, the voltage of the off switch 4 is
The breakdown voltage between the cathodes is suppressed below.

Therefore, the fall dig/dt of the gate current tends to become small.

Conventionally, in order to make dig/dt as large as possible and to exceed the specified value required for GTO turn-off, a high-speed semiconductor switch was used as switch 6, and measures were taken not to lower the wiring accelerator. This is a major bottleneck in circuit design.

Also, when connecting multiple GTOs in series or in parallel, the turn-off time. It is necessary to keep the turn-off time within a certain range. However, if dig/dt is small, the accumulation time of the turn-off time (excess carriers are removed from the p base layer of the GTO, current concentration occurs in the p base layer directly under the center of the n emitter, and the J2 junction This results in large variations in the time it takes for a depletion layer to form, resulting in a disadvantage that a desired device cannot be obtained.

Therefore, an object of the present invention is to provide a gate circuit that can increase dig/dt.

1Σ1 Means for Solving the Problems The present invention sets the OFF power supply voltage to be higher than the breakdown voltage between the gate and the cathode in the OFF gate circuit of c'ro. In addition, resistors are connected between the gate and cathode and in parallel with the switch for supplying gate current, and when the GTO's cut-off current is at its maximum controllable on-current, the capacitance of the capacitor breaks down at the end of the storage time. The voltage and the capacitor voltage are selected and configured so that they are approximately the same.

When the switch is turned on during F2 action turn-off, a large current of dig/dt flows through the GTO at a voltage higher than breakdown, and the turn-off operation begins. 4 Accumulation time and tail time (
Tilmi flow flows due to residual carriers in the n-base layer,
When the amount of residual carriers decreases to approximately 6, the switch is turned off when the time is approximately equal to the sum of J and the period until the junction recovers. Thereafter, a slight reverse voltage is applied between the gate and the cathode until the ON signal is applied.

G. Example An embodiment of the present invention will be described in detail below based on FIG.

In this figure, the same parts as in FIG. 4 are designated by the same reference numerals, and their explanation will be omitted.

lO is the power supply for turning off, this power supply! The zero voltage is selected to be greater than the breakdown voltage.

Reference numeral 11 denotes a capacitor for generating an off gate current, which is connected in parallel with the off power source IO via a resistor 15. Note that the capacitance of this capacitor 11 is GTO3
When the cut-off current is the maximum controllable on-current, the breakdown voltage of the gate and the capacitor voltage are selected to be approximately the same at the end of the storage time. Reference numeral 12 denotes a monostable operating circuit, which is connected between the logic 2 and the switch 6, and generates an output for a certain period of time approximately equal to the sum of the accumulation time and the till time when it receives an ON command from the logic 2.

13 is a reverse bias resistor provided between the gate and cathode of the GTO, and 14 is a reverse bias resistor provided in parallel with the switch 6.

Next, its operation will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows each waveform when the cut-off current of the GTO 3 is the maximum controllable on-current, where Va is the anode voltage and Ia is the anode current. When the GTO3 is in the OFF state, the monostable operation circuit 12 generates an output at time L1 according to a command from the logic unit 2, and when the switch 6 is turned on, a gate current ig flows through the route of the capacitor 11, the switch 6, the cathode of the GTO3, and the gate. . At this time, the gate current is in a state where it easily flows because the voltage of the off power supply 10 is set higher than the breakdown voltage of the gate, and a large dig/dt can be obtained. When the time reaches the end of the GTO accumulation time,
The capacitor voltage Vc and the gate voltage g are approximately the same voltage. When time T passes and time t3 arrives, the monostable operation circuit 12
There is no output, and the switch 6 is turned off. Therefore, the gate voltage g suddenly shifts to zero, but if the voltage E of the power supply lO and the resistance values of the resistors 13 to 15 are R, , R, R, respectively, then the current flows. This is the point in time.

FIG. 3 is a waveform diagram when the G TO cutoff current is small.

When the switch 6 is turned on at time [1, the time is set, and at G
The current 1a flowing through 'rO3 begins to be cut off, but
At this time, since the current flowing through the gate is small, the capacitor voltage vc is higher than the breakdown voltage of the gate. Therefore, the gate current ig continues to flow, and at time t3 becomes equal to the capacitor voltage VC minus the breakdown voltage ge, and the gate current ig begins to decrease. Time T has passed since time t1,
At time [4], the output of the monostable operating circuit I2 disappears, so the switch 6 is turned off, and from then on, the switch 6 is turned off and maintained in the off state. At time t4, the power is turned on and the off state is maintained.

H. Effects of the Invention According to the present invention, the OFF voltage is set higher than the breakdown voltage for a certain period of time.
Since the gate current is caused to flow based on this high voltage, a large dig/dt can be obtained, and the design of the OFF gate circuit becomes easy. In addition, since the peak current can be increased, the breaking performance of the GTO is improved. Furthermore, by increasing dig/dt, the turn-off time is shortened, and when GTOs are connected in series or in parallel, there is no imbalance in turn-off time, so the load is not placed on only some elements.
A device with balanced turn-off characteristics is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams for explaining the present invention, and FIG. 4 is a block diagram showing a conventional gate circuit. l... Gate current generation circuit for off, 2... logic section, 3... GTo, 6 - switch, lO... power source for off, 11... capacitor, 12... monostable operation circuit , 13-15...resistance. Figure 1: Present invention Figure 4: Conventional gate circuit

Claims (1)

[Claims] In a device in which an OFF power supply and a capacitor are provided in parallel, and an OFF current is supplied from this parallel circuit through a switch between the gate and cathode of a gate turn-off thyristor with reverse polarity, the OFF power supply voltage a monostable operation circuit whose voltage is higher than the breakdown voltage of the gate and which is placed between the switch and a logic section for controlling the switch and outputs a signal for a certain period of time, and the gate of the gate turn-off thyristor.・Resistors are connected between the cathodes and in parallel with the switch, and furthermore, when the gate turn-off thyristor's breaking current is near the maximum controllable current, the breakdown voltage of the gate and the capacitor voltage are made to be approximately the same near the end of the accumulation time. A gate circuit for a gate turn-off thyristor characterized by a selected capacitor capacity.