JPH02137327A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a second layer interconnection from being disconnected stepwise by conducting an isotropic dry etching and an anisotropic dry etching continued thereto in one dry etching step to form a wiring having a stepped cross-section. CONSTITUTION:A first aluminum interconnection layer 3 covering a semiconductor substrate 1 is coated with photoresist to form a photoresist layer 6. The layer 6 is exposed with a photomask 7. Then, the layer 3 is isotropically dry etched except a predetermined thickness in a first etching step. Then, the remaining film of the layer 3 is anisotropically dry etched to form first aluminum interconnection 3a. Thereafter, after it is covered with an interlayer insulating film 4, the whole face is sputtered with aluminum, the aluminum layer is then etched in a predetermined pattern by anisotropically dry etching to form a second aluminum interconnection 5. In this case, the interconnection 5 is not stepwisely disconnected to be formed by crossing with the interconnection 3a since the cross-section of the first layer interconnection 3a is stepped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having two or more multilayer interconnections.

[Conventional technology]

Conventionally, a method for manufacturing a semiconductor device having this type of multilayer interconnection structure has been, for example, as shown in FIG.
A first aluminum wiring 3a is formed thereon by anisotropic dry etching with an insulating film 2 such as SiO□ interposed therebetween. At this time, the cross section of the wiring 3a was rectangular or square (
Figure 3(A)). Next, 5i(h
The second layer aluminum wiring 5 was formed by vapor deposition or sputtering via the interlayer insulating film 4 (FIG. 3(B)), or as shown in FIG. The cross-sectional shape of 3a was made into a step-like shape by two exposure steps through photosensitive resin (so-called photoresist) 8c and 6d and two times of anisotropic dry etching.
Figures (A), (B)).

[Problem to be solved by the invention]

The method for manufacturing a semiconductor device having the conventional multilayer wiring structure described above is based on the method shown in FIG.
This method has a disadvantage in that, as shown in FIG. 3(B), a break occurs in the second aluminum wiring 5 at the shoulder portion 4a of the interlayer insulating film 4 arising from the end of the first aluminum wiring 3a.

Further, according to the method shown in FIG. 4, the steepness of the upper portion of the first aluminum wiring 3a is alleviated, and breakage of 50 stages of the second aluminum wiring can be avoided. However, with this method, 2
It takes a lot of man-hours because it requires multiple exposure steps, pattern misalignment occurs when the mask is applied twice, and the step width d of about 3 to 5 μm is required to create a step shape. There were drawbacks such as difficulty in forming fine patterns of aluminum wiring due to higher integration.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention involves forming a mask for etching a desired pattern on a wiring layer, isotropically dry etching the wiring layer to a predetermined thickness using the mask, and then using the mask to dry-etch the wiring layer to a predetermined thickness. The method is characterized in that anisotropic dry etching is performed to form wiring having a step-like cross-sectional shape.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view of each step showing the first embodiment of the present invention in order of steps. For example, a photoresist is coated on a first aluminum wiring layer 3 formed on a semiconductor substrate 1 on which an integrated circuit or the like is formed via an insulating film 2 such as 5i (h) to form a photoresist layer 6. In this case, a so-called positive type photoresist is used, but a negative type photoresist can also be used.Then, this photoresist layer 6 is exposed to light using a photomask 7. 6a changes and becomes soluble in the developer (see Figure 1 (A)).
)). Next, this photoresist layer 6 is developed to remove the exposed portion 6a, and the first aluminum wiring layer 30 is removed.
A predetermined pattern of photoresist 6c is formed on the surface (Fig. 1 (B)).

Next, using a parallel plate type reactive ion etching device using, for example, a photoresist (6c) as a mask, the pressure conditions were set to 80°C.
mTorr, RF power condition of 500 W, and gas condition of boron trichloride (BCA3), chlorine (Cn*), and oxygen (0,) flow rate ratio of 40:8:1 to form the first aluminum wiring layer 3 to a predetermined thickness. Isotropic dry etching is performed as the first step, leaving only the thickness (for example, about 1/3 of the original film thickness) (see Figure 1 (C).Subsequently, when the isotropic dry etching is completed, While the semiconductor substrate 1 was kept in a vacuum in the etching chamber, the pressure condition was set to 40 mTorr for the second step of etching.

The first aluminum wiring layer 3 was heated with an RF power of 800 W and a gas condition in which the flow rate ratio of boron trichloride, chlorine, trifluorocarbon (CHF s ), and nitrogen (N2) was 45:4:2:1. The remaining film is anisotropically dry etched, and the first
Aluminum wiring 3a is formed (FIG. 1 (D)).

Next, in the state shown in FIG. 1(D), the semiconductor substrate 1 is placed in a plasma ashing device, and photoresist is processed using oxygen plasma.
6c is incinerated and removed. After that, an interlayer insulating film 4 of 5iOz or the like is deposited on the entire surface including the first aluminum wiring 3a by the CVD method, and then aluminum is sputtered on the entire surface, and then this aluminum layer is etched into a predetermined pattern by anisotropic dry etching. A second aluminum wiring 5 is formed by etching. Since the cross section of the first layer wiring 3a is step-shaped, the second layer wiring 5 can be connected to the first layer without any breakage.
It is formed to intersect with the wiring 3a of the layer (FIG. 1(E)).
. It should be noted that the present invention is not limited to the above-mentioned embodiments, but can also be a multilayer wiring of three or more layers. In this case, all of the lower layer wiring is made to have a stepped cross section using the method described above.

FIG. 2 is a cross-sectional view of each step showing the second embodiment of the present invention in order of steps. For example, a predetermined pattern of photoresist is formed on a tungsten wiring layer 8 formed on a semiconductor substrate 1 on which an integrated circuit or the like is formed via an insulating film 2 of 5iOz, etc. through resist coating, alignment, exposure, and development processing steps. )6c
(Fig. 2 (A), (B)).

Next, for example, using a parallel plate type reactive ion etching apparatus, the tungsten wiring 8 is etched using the photoresist 6c as a mask under a pressure condition of 1 5 Q mTorr.

RE power condition is 500W, gas condition is sulfur hexafluoride (
SFs) and fluorochlorocarbon gases (e.g. C*C
Isotropic dry etching is performed as the first step, leaving only a predetermined thickness (for example, 1/2 of the original film thickness) at a flow rate ratio of 2:1 (Fig.
C)). Next, for the second step of etching, the pressure condition was 150 mTorr, and the power condition was set to R.
ow, the remaining film of the tungsten wiring layer 8 is anisotropically dry etched under gas conditions where the flow rate ratio of fluorochlorocarbon gas (for example, CxCJxFs) and nitrogen (N2) is 3:1, and the tungsten wiring 8a is (second
Figure (D)).

Next, after removing the photoresist (6c) using a plasma ashing device, an interlayer insulating film 4 such as Sin is deposited on the entire surface including the tungsten wiring 8a by the CVD method, and aluminum is sputtered on the entire surface. This aluminum layer is etched into a predetermined pattern by anisotropic dry etching to form aluminum wiring 9 (see FIG. 2(E)).
).

In this second embodiment, the tungsten wiring, which has a lower electromigration and stress migration failure rate than aluminum wiring and is said to have a longer wiring life, can be made into a stepped shape.
There is an advantage that fine patterning of LSI (LSI after bit DRAM) becomes possible.

〔Effect of the invention〕

As explained above, when forming the first layer wiring, the present invention uses a dry etching step using a predetermined pattern of photoresist as a mask, and then performs isotropic dry etching followed by anisotropic dry etching using a pre-etching method. 1 dry etching
This process is performed in multiple dry etching steps to form wiring with a step-like cross section.

This has the effect of preventing breakage of the second layer wiring formed on the first layer wiring layer with an insulating film interposed therebetween.

Furthermore, according to the above-described manufacturing method, the most labor-intensive exposure step when forming the second layer wiring having a step-like cross-sectional shape can be performed only once, thereby significantly reducing the number of manufacturing steps and improving work efficiency. In addition, since the exposure process only needs to be done once, defects caused by this are less likely to occur.Furthermore, since there is no need for the conventional two-time mask alignment, wiring with a stepped cross section can be formed with high accuracy without pattern misalignment. be. Furthermore, by controlling the amount of isotropic dry etching, it becomes possible to narrow the stepped step width d to the submicron level, making it possible to form fine patterns in the next generation of multilayer wiring.

8a... Tungsten wiring, 9... mark aluminum wiring.

Claims (1)

[Claims] An etching mask with a predetermined pattern is formed on the wiring layer formed on the semiconductor substrate, the wiring layer is isotropically dry etched to a predetermined thickness using the mask, and then anisotropic dry etching is performed using the mask. 1. A method for manufacturing a semiconductor device, comprising etching to form wiring having a stepped cross-sectional shape.