JPH02143614A - Echo elimination type transmitter - Google Patents

Abstract

PURPOSE:To simplify the constitution by applying transmission synchronously with a transmission clock generated synchronously with a host clock, correcting a pseudo signal in response to a phase deviation of a transmission and a reception clock and eliminating echo. CONSTITUTION:A transmission circuit 3 converts a transmission digital signal 2 into a transmission analog signal 4 synchronously with a transmission clock 20. If jitter takes place in the signal 4, the transmission synchronously with a network clock 13 is applied. On the other hand, an A/D converter 8 of a reception system applies AD conversion to a received analog signal 7 synchronously with a reception clock 21 to generate a reception digital signal 9, an echo elimination circuit 22 eliminates echo replica from the signal 9 and a reception circuit 11 outputs a received digital signal 12 to a digital switch circuit network. If jitter takes place in the clock 20, the circuit 11 outputs timing information 18 and a receiver side DPLL 26 matches the timing of the clock 21 with the clock 20 based on the information 18 to attain the reception in following to the clock 20, that is the clock 13.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an echo cancellation type transmission device that performs bidirectional transmission of digital signals and analog signals using a full-duplex communication method, and is particularly applicable to a network synchronization method, etc. This relates to a system that operates using an upper clock.

[Conventional technology]

In recent years, the communication network has been changed to the Integrated Service Digital Network (ISDN).
To facilitate this development, echo-canceling transmission devices have been developed. According to this echo canceling type transmission device, it is possible to introduce a digital transmission system based on a full duplex communication system using an existing two-wire subscriber line.

FIG. 2 shows a conventional echo cancellation type transmission device.

As shown in the figure, an echo canceling type transmission device 1 is installed in each subscriber circuit in a telephone office, and is usually constructed using digital signal processing in order to stabilize quality.

A transmitted digital signal 2 from the digital switch network side is converted into an analog signal 4 by a transmitting circuit 3, and transmitted to a two-wire subscriber line 6 by a hybrid circuit 5. On the other hand, a received analog signal 7 received by the hybrid circuit 5 from the two-wire subscriber line 6 is input to an A/D (analog/digital) converter 8 and converted into a received digital signal 9. After the echo of the transmitted digital signal 2 contained in the received digital signal 9 is removed by an echo removal circuit 10, the received digital signal 9 is transmitted to the digital switch network side as a received digital signal 12 by a receiving circuit 11.

Next, the synchronization system will be explained. Based on the dependent synchronization method in network synchronization, this echo canceling type transmission device 1 operates in synchronization with a network clock 13 transmitted from a synchronous network.

That is, the network clock 13 received from the synchronous network is processed by the analog phase locked loop (APLL) 14 in the telephone office.
A high frequency operating clock 15 with transmission jitter corrected is generated, and this operating clock 15 is distributed to each echo cancellation type transmission device 1.

In each echo cancellation type transmission device 1, the transmission circuit 3 processes the transmission digital signal 2 in synchronization with the operation clock 15. Regarding the reception digital signal 12, a reception clock 18 is generated by adapting the timing to the operation clock 15 using a reception digital phase synchronization circuit (DPLL>16) based on the timing information 17 from the reception circuit 11, and this reception clock 18, the A/D converter 8, the echo cancellation circuit 10, and the receiving circuit 11 perform processing.

The operating clock 15 preferably has a frequency of about 200 times or more the transmission baud rate in order to keep timing jitter generated by the receiving DPLL 16 to a minimum. For this reason, for example, in a transmission system using the 2BIQ coding system, 80
When performing board line rate transmission, the frequency of the operating clock 15 is 16 MHz, and the A M
(Alternate~1ark [nversion
) code transmission system (line relay), 160Kbps
, the frequency of the operating clock 15 is 32M.
It becomes Hz.

In addition, in order to compensate for the deterioration of echo cancellation characteristics caused by the digital phase jump of the operating clock 15, the amount of echo replicas is adjusted according to the phase lead or lag of one reference clock (hereinafter referred to as phase jump). A method of adding a jitter compensation filter to the echo cancellation circuit has also been proposed (11 Compensa
tion for the Residual Echo
Increase due to a Timing
C1ockPhase Jump, Procee
ding Globecom '87. Match.

See November 1987.

[Problem to be solved by the invention]

Generally, the echo cancellation type transmission device 1 is mounted on a printed wiring board, and a plurality of the printed wiring boards are mounted on a shelf. For this reason, in the conventional configuration described above, since the operating clock 15 has a high frequency of 10 MHz or more, there is a problem in that waveform distortion occurs in the operating clock 15 when it is distributed to each echo cancellation type transmission device 1.

This problem can be avoided by directly distributing the network clock 13 to each echo canceling type transmission device 1 and creating the operating clock 15 within each echo canceling type transmission device 1. However, in such an embodiment, the relatively expensive APLL 1
4 must be placed in each echo-canceling transmission device 1, and considering the manner in which the echo-canceling transmission device is used by being incorporated into a subscriber circuit, this significantly impedes the cost of the entire device. This is not practical.

In view of these problems, it is an object of the present invention to provide an echo cancellation type transmission device that can directly distribute an upper clock and has a simple configuration that does not use APLL.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention provides an echo cancellation type transmission device having the following means.

(1) Reference clock generation means for generating a reference clock with a higher frequency than the input higher-order clock.

(2) Transmission clock generation means for generating a transmission clock synchronized with the upper clock based on the upper clock and the reference clock.

(3) A transmitting means that operates in synchronization with the transmitting clock and converts the transmitting digital signal transmitted from the full-duplex communication digital transmission line into a transmitting analog signal and transmitting the analog signal to the analog transmission line.

(4) Receive clock generating means that generates a receive clock based on the reference clock, corrects the timing of the receive clock based on timing information, and outputs the corrected timing.

(5) Operates in synchronization with the reception clock, converts the reception analog signal received from the analog transmission line into a reception digital signal, transmits it to the full-duplex communication digital transmission line, and synchronizes the reception clock with respect to the transmission clock. Receiving means that detects the deviation and outputs timing information.

(6) Generate a pseudo-echo signal based on the transmitted digital signal, correct the pseudo-echo signal in accordance with the deviation between the transmitted clock and the received clock, and further subtract the corrected pseudo-echo signal from the received digital signal. Echo removal means.

[Effect]

According to the echo cancellation type transmission device according to the present invention, the transmission clock generation means generates a transmission clock synchronized with the upper clock, and the transmission means performs a transmission operation in synchronization with the transmission clock. Therefore, it is sufficient to directly input the higher-order clock to the echo cancellation type transmission device, and there is no need to input a high-frequency clock.

Also, the reception clock generation means generates the reception clock while correcting the timing based on the timing information indicating the deviation from the transmission clock, and the reception means performs the reception operation in synchronization with this. Reception operations can be performed in synchronization with the clock.

When jitter occurs in the upper clock, a temporary deviation occurs between the transmitting clock and the receiving clock, but the echo removal means corrects the pseudo echo signal in response to this deviation and then performs the echo removal operation. , the echo cancellation ability can be ensured. As described above, the deviation of the reception clock with respect to the transmission clock is immediately corrected by the reception clock generation means.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows an echo cancellation type transmission device according to an embodiment of the present invention. This echo cancellation type transmission device 19 converts the transmitted digital signal 2 and the received digital signal 12 to the digital switch network and the analog signal to the two-line subscriber line 6, and converts the network clock 13 from the synchronous network. It operates based on the following.

The transmitting circuit 3 operates in synchronization with the transmitting clock 20 and converts the transmitting digital signal 2 into a transmitting analog signal 4. The no-brid circuit 5 transmits the transmitted analog signal 4 to the two-line subscriber line 6 and receives the received analog signal 7 from the two-line subscriber line 6. The A/D converter 8 samples the received analog signal 7 at a timing based on the reception clock 21 and converts the received analog signal 7 into an A/D converter 8.
It performs D conversion and outputs a received digital signal 9. The echo cancellation circuit 22 generates an echo replica based on the transmission digital signal 2, and also generates an echo replica based on the transmission clock 2.
0 and the reception clock 21, that is, the phase lead or delay of one clock of the reference clock 23, the amount of echo replicas is corrected, and the amount of echo replicas is subtracted from the reception digital signal 9 based on the corrected echo replica. It is intended to provide

Correction of echo replicas will be described later. Receiving circuit 1
1 transmits a received digital signal 12 based on the output of an echo canceling circuit 22, and also outputs timing information 18 indicating the phase shift between the aforementioned transmitting clock 20 and receiving clock 21.

The reference clock generator 24 independently generates a reference clock 23 having a frequency of about 200 times the transmission baud rate with respect to the network clock 13.

Based on the reference clock 23, the transmitting DPLL 25
It generates a transmission clock 20 that follows the network clock 13. The receiving DPLL 26 receives timing information 1
The receiving clock 21 is generated based on the reference clock 23 while adjusting the timing by one clock of the reference clock 23 according to the reference clock 23.

In the above configuration, the transmitting circuit 3 has a transmitting clock 20
Transmit digital signal 2 in synchronization with transmit analog signal 4
will be converted into The transmission clock 20 is the network clock 13
Although jitter occurs in the transmitted analog signal 4, it is possible to perform a transmission operation accurately synchronized with the network clock 13.

On the other hand, the receiving system operates in synchronization with the receiving clock 21. That is, in synchronization with the reception clock 21, the A/D converter 8 A/D converts the reception analog signal 7 to create the reception digital signal 9, and the echo removal circuit 22 removes echo replicas from the reception digital signal 9. , receiving circuit 11
outputs the received digital signal 12 to the digital switch network side.

When the above-mentioned jitter occurs in the transmission clock 20, the reception circuit 11 outputs the timing information 18, and the reception side DPLL 26 matches the timing of the reception clock 21 with the transmission clock 20 based on the timing information 18. A reception operation that follows the clock 20, that is, the network clock 13, is performed.

Furthermore, since an error occurs in the echo replica when the above-described phase shift occurs, the echo removal circuit 22 corrects the echo replica based on the phase shift and then subtracts it from the received digital signal 9.

This can prevent characteristic deterioration of the echo removal circuit.

Generally, there is a phase shift Δ1 in the sampling timing of the received analog signal 7. The echo replica correction amount ΔR for
is expressed by the following formula. Here, he is the impulse response of the echo waveform, A7 is the symbol, and T is the sampling time interval.

(2) Therefore, it is possible to configure an echo replica correction filter by commonly using the thick correction filter A for the tap coefficients.

Further, the correction amount Δr of the echo replica with respect to the phase shift Δ1s in the transmission timing is given by the following equation, considering that only the symbols after the symbol transmitted when the phase shift occurs are affected. However, al is valid only for the transmitted symbols after the phase shift Δt has occurred, and is 0 otherwise.

n=-ooat As explained above, according to this embodiment, for the echo cancellation type transmission device 19 that is mounted in parallel, the normal 8KH
It is only necessary to distribute network clocks 13 of about z, which has the advantage of avoiding problems associated with conventional high frequency clock distribution. Moreover, the reference clock generator 2
4, that is, it can be constructed by simply adding a relatively inexpensive oscillator that generates an independent clock to the network clock 13, so there is an advantage that it can be realized by low-cost improvement.

〔Effect of the invention〕

As explained above, according to the echo cancellation type transmission device according to the present invention, a transmission clock synchronized with the upper clock is generated internally, and a transmission operation is performed in synchronization with this transmission clock, so that the echo cancellation type transmission device according to the present invention The upper clock may be input directly to the transmission device.

Therefore, it is possible to avoid the conventional problems associated with high frequency clock distribution.

Furthermore, since the echo removal operation is performed after correcting the pseudo echo signal due to the phase shift between the transmission clock and the reception clock, there is an effect that the echo removal ability can be ensured.

Furthermore, since it can be realized with a simple configuration that does not use APLL, it has the effect of being economically advantageous.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an echo cancellation type transmission device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional echo cancellation type transmission device. 2...Transmission digital signal, 3...Transmission circuit, 4...Transmission analog signal, 5...Hybrid circuit, 6...2 Line subscriber line, 7... Received analog signal, 8... A/D converter, 9... Received digital signal, 11... Receiving circuit, 12... Received digital signal, 13...
-Network clock, 18...timing information, I9...echo cancellation type transmission device, 20...
...Transmission clock, 21...Reception clock, 22...Echo removal circuit, 23...Reference clock, 24...Reference clock generator, 25.・・・・・・
- DPLL for transmission. 26... DPLL for reception.

Claims (1)

[Scope of Claims] A reference clock generating means for generating a reference clock having a higher frequency than an input higher-level clock; and a transmitting clock generating means for generating a transmitting clock synchronized with the higher-level clock based on the higher-level clock and the reference clock. , a transmitting means that operates in synchronization with a transmitting clock and converts a transmitting digital signal transmitted from a full-duplex communication digital transmission line into a transmitting analog signal and transmitting it to the analog transmission line; and a receiving clock based on a reference clock. and a reception clock generation means that corrects the timing of the reception clock based on the timing information and outputs it, and a reception clock generation means that operates in synchronization with the reception clock and converts the reception analog signal received from the analog transmission line into a reception digital signal. a receiving means for converting and transmitting the converted digital signal to a full-duplex communication digital transmission line, detecting a deviation of the receiving clock with respect to the transmitting clock and outputting timing information; and generating a pseudo echo signal based on the transmitted digital signal; An echo cancellation type transmission device characterized by comprising an echo removing means for correcting a pseudo echo signal in response to a deviation between a transmitting clock and a receiving clock, and further subtracting the corrected pseudo echo signal from a received digital signal. .