JPH02159999A - step motor drive circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a step motor drive circuit that detects the rotational state of a step motor and corrects the rotation.

(Prior art and its problems) As an example of step motor drive, when we look at the drive of a step motor in an electronic wristwatch with an analog display, the load driven by the step motor is not constant. When driving the display calendar mechanism, a larger load than usual will be applied to the step motor.Furthermore, take into account that the step motor's driving ability will decrease due to changes in battery voltage over time or a drop in voltage due to a drop in ambient temperature. Then, in order to reliably drive the step motor under these conditions, it is necessary to supply a drive waveform with a certain margin added to the drive waveform required to drive the maximum load.

However, when the step motor is driven in the manner described above, the calendar mechanism is not driven - during most of the day and under normal temperature conditions, more power is required to rotate the step motor than is required to rotate the step motor. A drive current will be supplied, and the current will be wasted.

To solve these problems, for example,
No. 6400 discloses that a driving pulse with a narrow pulse width that can be rotated under normal driving conditions is supplied to a step motor, and when it is detected whether or not the step motor actually rotates, and when the step motor is not rotating, a drive pulse with a narrow pulse width that can be rotated under normal driving conditions is supplied. A technique has been disclosed that aims to reduce power consumption by supplying a drive pulse with a pulse width.

However, in the conventional drive method described above, when the step motor does not rotate, a drive pulse for correction is supplied within one cycle of the drive pulse or in the next cycle. The pulse motor rotates twice in about one cycle, causing the hands that display the time to move irregularly, resulting in a problem in which the user misunderstands that there is a malfunction in the watch itself. For example, if a non-rotation occurs in the second hand driven by a signal with a 1-second period, even if a drive pulse for correction is supplied immediately after detecting the non-rotation, the time interval between the hand movement and the next 1-second signal becomes short (and the hands move as if they are malfunctioning).

Furthermore, recently, some electronic watches with analog display have been designed to notify the end of the battery life by, for example, moving the second hand twice in succession every two seconds when the battery life approaches its end. In this type of electronic watch, it is difficult to distinguish between the irregular hand movements caused by the drive pulses for correction when the step motor is not rotating, as described above. There is also the problem that correction of non-rotation of the step motor may be mistakenly determined to mean that the battery life has been reached.

[Object of the Invention] An object of the present invention is to provide a step motor drive circuit that can correct the rotation without causing irregular rotation when non-rotation of the step motor is detected.

[Key points of the invention]

The present invention provides the step motor with a drive signal (first drive signal) that can be driven under normal load conditions and environmental conditions, and when the step motor does not rotate due to the drive signal, the frequency dividing means By controlling the frequency division ratio of the synchronous signal to shorten the period of the synchronizing signal, and further supplying the step motor with a second drive signal for correction created based on the synchronous signal with the corrected period, the rotation speed can be reduced. This is for making corrections.

[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 8.

FIG. 1 is a diagram showing the circuit configuration of an analog display electronic wristwatch according to a first embodiment of the present invention. In the figure, an oscillation circuit 1 includes, for example, a crystal oscillator, generates a reference clock signal of 32.768 KHz, and outputs it to the first frequency dividing means 2. The first frequency division stage 2 divides the frequency of the above reference clock signal into 32
] (Creates a signal of
The frequency is divided and a 16 Hz signal is output to the third frequency division stage 4. The third frequency dividing means 4 further divides the 16 Hz signal into a 1 Hz signal (signal a), and outputs it to the first waveform output section 5, the second waveform output section 6, and the one-shot circuit 15.

The first waveform output unit 5 and the second waveform output unit 6 generate signals b and C with different pulse widths (different duties) based on the signal a from the third frequency division stage 4, and output them to an AND gate 7. and 8, and the signal C from the second waveform output section 6 is a signal with a wider ON width than the first waveform output section 5.

The Q output signal and the Q output signal of the RS flip-flop 13 are input to the other input terminals of the AND gates 7 and 8, respectively, and the outputs of the AND gates 7 and 8 are input to the waveform shaping section 9.

The waveform shaping section 9 generates two types of signals e and 2 having a phase difference of 180 degrees from each other based on the signal d from the first waveform output section 5 or the second waveform output section 6 applied via the AND gate 7 or 8. This is a circuit that creates r. Since the RS flip-flop 13 is in the reset state when the step motor is rotating normally, the waveform shaping section 9 receives a signal with a narrow ON width from the first waveform output section 5 via the AND gate 7. (Signal b) is human-powered, and the step motor is normally driven by a signal with a narrow ON width in a drive circuit 10, which will be described later.

The drive circuits 10 are connected at 180° to each other from the waveform shaping section 9.
Alternately switching the direction of the excitation current supplied to the stator coil lla based on the signals e and f having a phase difference of
This is a circuit that controls the drive of the step motor 11. The drive circuit 10 includes, for example, as shown in FIG. 2, a P-channel transistor 21 and an N-channel transistor 22 are connected in cascade, and a P-channel transistor 23 and an N-channel transistor 24 are also connected in cascade. configured. By applying signals e and r having a phase difference of 180° to the drive circuit 10 in FIG. 2, the transistors 2 arranged diagonally in FIG.
1 and 24, or transistors 23 and 24 are turned on and off alternately to turn on and off the stator coil 11.1 of the step motor 11. The direction of the excitation current supplied to a can be switched.

The step motor 11 includes a stator coil lla, a stator 11b which is alternately excited with opposite polarity by the stator coil lla, and a rotor llc which is made up of a permanent magnet arranged opposite to the stator 11b and magnetized into two poles. The rotation of the rotor 11c is transmitted to the hour hand, minute hand, and second hand via a gear train mechanism (not shown), and is further transmitted to a calendar mechanism that displays the day of the week and date.

Further, the stator coil 11a of the step motor 11 is provided with a rotation detection section 12 for detecting whether the rotor llc actually rotates when the step motor 11 is driven by supplying an excitation current. The rotation detection unit 12 detects whether or not the rotor 11c rotates normally based on the current induced in the stator coil lla due to the rotation of the rotor 11c. At times, a high level detection signal g is output to the RS flip-flop 13.

The Q and Q output signals of the RS flip-flop 13 are input to AND gates 7 and 8, and turn the above-mentioned AND gates 7 and 8 on or off. For example, when the step motor 11 rotates normally, the RS flip-flop 13 maintains the recent state, the AND gate 7 opens, and the first
A signal created based on the signal with a narrow ON width created by the waveform output section 5 is input to the waveform shaping section 9, and the step motor is driven by the signal.

On the other hand, when the rotation detecting section 12 detects that the step motor 11 does not rotate, the RS flip-flop 13 is set by the high level detection signal g.

Due to the dirt, the Q output signal becomes high level, the AND gate 8 opens, and the waveform shaping section 9 converts the drive signal e and r is created, and drive energy larger than normal is supplied to the step motor 11.

Also, I'? S flip flop 13. The Q output signal is inputted to an AND gate 14, and the output of this AND gate 14 is inputted to the second frequency division stage 3 and the 32-decimal counter 16. The other input terminal of the AND gate 14 is given a signal i with a period of 1 second from the one-shot circuit 15,
When the rotation detection unit 12 detects non-rotation and the RS flip-flop 13 is set, the signal i is output to the AND gate 1.
4 and then input to the second frequency division stage 3. The second frequency dividing stage 3 is preset by the above signal i, and it counts one pulse more than the original number of pulses from the first frequency dividing stage 2. 1 pulse (1
/32 seconds), the signal is output earlier and applied to the third frequency dividing stage 4.

Then, a signal (signal a) with a cycle 1732 seconds earlier is output from the third frequency dividing stage 4, and a signal i synchronized with the signal a is given again to the second frequency dividing stage 3 via the AND gate 14. Similarly, a signal whose cycle is one pulse (1/32 second) earlier is output from the third frequency dividing stage 4.

The 32-decimal counter 16 is a counter that counts 32 times the period correction at the second frequency division stage 3, and the AND gate 14
When the signal from the step motor 11 is counted 32 times and the correction for one rotation of the step motor 11 is completed, a carry signal is output and the RS
Reset the flip-flop 13.

That is, when the rotation detecting section 12 detects non-rotation of the pulse motor 11, G- is given a pulse to the second frequency dividing stage 3 every cycle of the signal a output from the third frequency dividing stage 4, The second frequency dividing stage 3 outputs a signal (in this embodiment, a signal whose one round is 31/32 seconds) one pulse earlier than the original number of pulses. Furthermore, the above cycle correction is repeated 32 times,
The third frequency dividing stage 4 outputs 33 signals a for 32 seconds. Therefore, by driving the pulse motor 11 based on this signal a, correction for one non-rotation can be performed.

Also, at this time, the signal C with a wide ON width created by the second waveform output section 6 passes through the AND gate 8 and is output to the waveform shaping section 9, so the period is corrected from the waveform shaping section 9 as described above. Signals e and f with wide on-width are given as drive signals, and these signals drive the step motor 1.
1 rotation correction is performed.

Next, the circuit operation of the embodiment configured as above will be explained with reference to the timing chart of FIG.

When the step motor 11 is operating normally, the third frequency dividing stage 4 outputs a signal a with a period of 1 second as shown in FIG. , for example, generates and outputs a signal with the minimum ON width that can drive the hour hand, minute hand, and second hand simultaneously. In this state, the waveform shaping section 9 outputs signals e and r having the same on-width as the above signal and having a phase difference of 180° (signals e and f in Fig. 3).
left half).

On the other hand, if the step motor 11 does not rotate normally for some reason and the rotation detector 12 detects non-rotation, the rotation detector 12 sends a high-level detection signal g (signal g in FIG. 3) with a constant width to the RS. It is output to the set terminal of the flip-flop 13. This detection signal g causes the RS flip-flop 13 to
is in the set state, the output signal of the Q output terminal becomes high level (signal h in Figure 3), and the one-shot circuit 15
The signal i outputted every second (less than one second when non-rotation is detected and corrected) from then on forces the second divider stage 3 to preset to "l".

As a result, the second frequency dividing stage 3 is given one extra pulse during one period of the 32Hz signal, and the third
The frequency dividing stage 4 outputs a signal a (the right half of the signal a in FIG. 3) having a cycle 1/32 seconds shorter than the normal one-second cycle.

Thereafter, a signal with a cycle shorter than 1 second is similarly output 32 times, 33 pulses are output in a period of 32 seconds, and one rotation of the step motor is corrected. Also, when non-rotation is detected, the second waveform output section 6 is used instead of the signal.
A signal C with a wider ON width than the signal created by is output to the waveform shaping section 9, and a drive pulse with a wider ON width is supplied to the step motor 11 (right half of signals e and f in Fig. 3). .

As described above, when the step motor 11 does not rotate normally due to an increase in load or a drop in power supply voltage, the frequency division ratio of the frequency division stage is controlled to supply a signal with a shorter cycle than during normal rotation. Therefore, unlike the conventional case where a correction signal is given separately from the normal drive signal, irregular rotation of the step motor 11 can be prevented and smooth rotation correction can be realized. .

Next, FIG. 4 is a diagram showing a circuit configuration of a second embodiment of the present invention for correcting the rotation of a step motor.

The figure shows, for example, a circuit of an electronic clock with an analog display.

The oscillator 41 generates a reference clock signal and outputs it to the frequency dividing circuit 42 . The frequency dividing circuit 42 divides the frequency of the clock signal to create a 2048 Hz signal and outputs it to the control section 43.

The control unit 43 executes time measurement processing, driving of the step motor 49, and processing of storing data indicating the calculation result, the operating state of the step motor 49, etc. in the register of the RAM 45 in accordance with the control program stored in the ROM 44.

The RAM 45 is provided with various registers as shown in FIG. Register A is 2048 from frequency divider circuit 42
It is a counter that counts Hz signals, and register C is 3
It is a counter that counts carry signals every 2 Hz, and the register M is the step motor 49 read from the ROM 44.
This is a register that stores the on time during driving. Also,
The register F is a counter that counts the number of times the step motor 49 stops rotating, and the register F is a counter that counts the number of times the cycle is corrected until the correction of one rotation is completed.

The RS flip-flop 46 in FIG. 4 is a circuit whose output state is switched according to a set signal or a reset signal from the control section 43, and outputs a Q output signal to the waveform shaping section 47 and the control section 43. The above RS flip-flop 46
The output signal is waveform-shaped by a waveform shaping section 47 and then input to a driver circuit 48 .

The driver circuit 48 is a circuit that creates a plurality of signals having a predetermined phase difference based on manually input signals and supplies them to the step motor 49.
If so, two types of signals with a phase difference of 180° are output.

The rotation detection unit 50 is a circuit that detects whether or not the step motor 49 actually rotates when a drive signal is applied to the step motor 49. For example, the rotation detects a stator coil (not shown) of the step motor 49. Rotation or non-rotation is determined by detecting the induced current. The detection result of the rotation detection section 50 is input to the set terminal of the RS flip-flop 51, and the Q output of the RS flip-flop 51 is input to the control section 43.

That is, when the rotation detecting section 50 detects non-rotation, the RS flip-flop 51 is set, and the control section 43 sets the R flip-flop 51.
By reading the output state of the S flip-flop 51,
You can tell if non-rotation has occurred. Further, when a non-rotation detection signal is read, a reset signal is output to reset the RS flip-flop 51 to the initial state.

Next, the processing operation of the second embodiment configured as above will be explained with reference to the flowchart of FIG.

Each time the 2048 Hz signal from the frequency dividing circuit 42 is input to the control unit 43, the following processing is executed. First, in step SI, 2048 Hz signals are sequentially counted in register A. Then, the value counted in the next step S2 is A=64
(corresponding to a 32 Hz signal), and when A=64, register C is incremented in step S3.

A 32 Hz signal can be obtained from the 2048H2 signal by the processing in steps 51-33.

After step S2 or step S3, the Q output signal of the RS flip-flop 46 is read in step S4, and it is determined whether the signal for driving the step motor 49 is on. When the ON signal is being output, a register N that counts the ON time of the step motor 49 is incremented, and further, in the next step S6, it is determined whether the value of the register N has reached a predetermined ON time M (the value of the register M). determine whether

Here, the register M stores a value corresponding to the shortest on time among a plurality of on time data stored in the ROM 44 as an initial setting, and stores the value corresponding to the shortest on time of the plural on time data stored in the ROM 44.
Until the malfunction (non-rotation) of No. 9 occurs, the step motor 49 is driven during the minimum ON time.

In this embodiment, the ROM 44 has M=5 as the on time M.
．． Four types of values are stored: 6, 7, and 8. For example, if register M is set to "5", register N is stored.
=5, that is, while the 2048 Hz signal is counted five times (2,44 m5), the on signal is output.

If it is determined in step S6 that N=M, the process proceeds to step S7, where the RS flip-flop 46 is reset and the step motor 49 is turned off. Then, in the next step S8, the register N is initialized to "0", and further, in step S9, an instruction signal X to start detection is output to the rotation detecting section 50.

If it is determined in step S4 that the Q output signal of the RS flip-flop 46 is not in the on state, the process moves to step SIO;
Determine whether the value of register C is C-25. C-2
If it is 5, the Q output signal of the RS flip-flop 51 is read in the next step Sll to determine whether non-rotation is detected.

Here, the reason for determining whether the value of register C is "25" is to read the rotation detection signal stored in the RS flip-flop 51 when the 32Hz signal is counted 25 times. For example, as shown in FIG. 7, rotation or non-rotation is determined at the timing of 25/32 seconds of a drive signal with a one-second period.

When non-rotation is detected in step S11, the register M storing the on-time is incremented in the next step 312 to extend the on-time of the drive signal. Furthermore, in step SMI, a register L that stores the number of period corrections is initialized to "0", and since one non-rotation is detected, a register F that stores the rotation of the non-rotation is incremented. Then, since the occurrence of non-rotation is stored, the process proceeds to step SI5 and the RS flip-flop 51 is reset.

If non-rotation is not detected in step 311, the process advances to step SI4, in which non-rotation is detected before and the value of register M is set for the minimum on-time (for example, M-
5) When the value is set to a larger value, the value of register M is decremented and the decremented value is set in register M.

If the determination in step S1° is not C=25, the process proceeds to step SI&, where it is determined whether the value of register F, which stores the number of non-rotation detections, is "1" or more. If F≧1, it is determined in the next step SP7 whether C=31, and if C-31, the register L is incremented in the next step 3111.

Then, in step S19, the value of the register L is "32".
” is reached.

If L=32, proceed to step 321 and register C.
, and in the next step S22, RS free
The amplifier flop 46 is set and the drive signal for the step motor 49 is turned on.

That is, by turning on the drive signal for the step motor 49 when the 32 Hz signal is counted 31 times by the register C, it is possible to supply the step motor 49 with a drive signal with a cycle 1732 seconds shorter than that during normal drive. .

Further, this cycle correction is repeated until the value of the register L that stores the number of cycle corrections reaches "32". That is, when the pulse motor 49 is driven 33 times in 32 seconds and the correction for one rotation is completed, the register -32
The process then proceeds from step S19 to step S2O, where register L is cleared, and register F, which stores the number of non-rotation occurrences, is decremented, and the process ends.

Further, if F≧1 is not determined in step SI6, that is, if the step motor 49 is rotating normally, the process proceeds to step S23 and it is determined whether C-32.

If one cycle of the 32 Hz signal has passed and C=32, the process proceeds to step S21 described above, where the register C is cleared and an ON signal is supplied to the step motor 49.

As described above, in the second embodiment, the step motor 49
When non-rotation is detected, the drive cycle is made shorter than normal rotation, and the step motor 49 is rotated the required number of times using the short cycle drive signal, thereby correcting the rotation. Rotation can be corrected,
Further, the correction cycle can be set arbitrarily.

In the first and second embodiments described above, when non-rotation occurs, a drive signal with a wider on-width (duty) is supplied to the step motor, but as shown in FIG. It is also possible to apply drive signals of different voltages with the same on-width during and during correction, and the step motor to be driven may be limited to a two-pole motor or may have the same polarity.

In addition, in the first embodiment, a second frequency dividing signal of 32Hz is used.
Although the frequency division of the frequency dividing stage 3 has been controlled, it is of course possible to control the frequency division ratios of other frequency dividing stages. For example, 8 Hz inside the third divider stage 4
If you control the frequency division of the circuit that divides the signal of 1 in 8 seconds,
The configuration of the counter can be simplified since it is possible to perform correction for the ° pulse and it is sufficient to provide a counter that counts 8 seconds.

Furthermore, in the above embodiment, when non-rotation occurs, a correction pulse with the same phase is output again, but if the next signal with a different phase of 1806 is directly supplied to the step motor as a correction pulse. , a circuit for outputting pulses of the same phase during correction is not required, and the circuit configuration becomes simpler.

In this case, the step motor is not driven by the next correction pulse and becomes non-rotating again, so for example, the 32-digit counter 1
4 may be replaced with a 64-decimal counter and correction for 2 pulses may be performed.

In the second embodiment, a drive signal for a predetermined on-time is determined from a pre-stored numerical value corresponding to a plurality of on-times (for example, M=5.6°7.8) and a supplied 2048Hz signal. The processing is not limited to the above processing, for example, it is possible to directly store the on-time of a drive signal in multiple registers, and then read out one of the on-times depending on the rotational state of the step motor. Then, the step motor may be driven according to the on time.

〔Effect of the invention〕

According to the present invention, even when the step motor does not rotate, the non-rotation can be smoothly corrected without causing irregular movement in, for example, a pointer driven by the step motor.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of the first embodiment of the present invention, FIG. 2 is a diagram showing an example of a drive circuit, FIG. 3 is a timing chart showing the operation of the circuit in FIG. 1, and FIG. 5 is a diagram showing the circuit configuration of the second embodiment of the present invention, FIG. 5 is a diagram showing the configuration of the RAM in FIG. 4, and FIG.
7 is a diagram showing the detection timing of the step motor in the circuit of FIG. 4, and FIG. 8 is a diagram showing an example of the drive pulse of the step motor. 3... Second frequency division stage, 5... First waveform output section, 6... Second waveform output section, 12... Rotation detection section, 13... RS flip-flop, 16... 3
binary counter. of

Claims (1)

[Scope of Claims] Frequency dividing means for dividing the frequency of a reference clock signal to generate a synchronization signal in predetermined time units; and a first drive signal for driving a step motor based on the synchronization signal of the frequency division means. a first signal output means for outputting a signal, a detection means for detecting rotation or non-rotation of the step motor, and when the detection means detects non-rotation of the step motor, controlling a frequency division ratio of the frequency division means. and correction means for correcting the period of the synchronization signal and correcting the rotation by supplying a second drive signal different from the first drive signal to the step motor based on the corrected period. A step motor drive circuit featuring: