JPH02186675A - High breakdown strength planar type semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor element, whose breakdown strength is nearly equal to that of a conventional one, in a simple process by a method wherein a first lightly doped layer and two or more second lightly doped layers are formed through a single doping process using a mask provided with openings different in width. CONSTITUTION:An oxide film mask 11 is formed on the surface of a wafer where a p<+>-type layer 2 has been formed. An opening 12 of the oxide film mask 11 is used for forming a p<->-type layer 6 of a first lightly doped layer and two or more openings 13 provided outside the opening 12 are used for obtaining p<->-type layers 7 of second lightly doped layers. Using the oxide film mask 11 patterned as above, p-type dopant ions are implanted. Then, the p<->-type layers 6 and 7 partially overlapping each other are obtained through thermal diffusion. At this point, the thermal diffusion is executed under such a condition that the mask width of a region sandwiched between the openings 12 and 13 of the oxide film mask 11 is made almost equal to the diffusion depth of thermal diffusion, whereby the p<->-type layer 7 region formed through multiple diffusion, as a whole, is lower than the p<->-type layer 6 in dopant concentration per unit area. A doped layer high in reverse breakdown strength can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a high breakdown voltage planar semiconductor element having a pn junction structure and a manufacturing method thereof.

(Prior art) As a high voltage planar pn junction diode,
The structure shown in the figure is known. This is due to the p-type layer 22 selectively diffused on the surface of the n-type layer 21, and this p÷
The basic structure includes an anode electrode 23 in contact with the type layer and a cathode electrode 25 disposed on the back surface of the n-type layer 21 via a low-resistance n-type layer 24. A p-type layer 26 is diffused as a first low impurity concentration layer so as to be continuous with the p-type layer 22 of the diode, and a second p-type layer 26 is further formed around the p-type layer 26 as a first low impurity concentration layer. An expanded number of p-1 type layers 27 are formed as low impurity concentration layers. p
An n+ type layer 29 for fixing the surface potential of the n- type layer 21 and an electrode 30 in contact therewith are formed at a position further away from the -1 type layer 27 by a predetermined distance. p-type layer 2
6 and the p-1 type layer 27, the electric field concentrated at the edge portion of the p medium type layer 22 is relaxed, and a high reverse breakdown voltage can be obtained.

Although the structure shown in FIG. 7 can obtain a high breakdown voltage, as a process for increasing the breakdown voltage, a p-type layer 26 with a low impurity concentration is formed using the first mask, and then a p-type layer 26 with a low impurity concentration is formed using the second mask. forming a p-type layer 27 with a lower impurity concentration,
This requires two mask processes. Therefore, there was a problem that the manufacturing process was complicated.

Similar problems arise with other devices that include similar p-n junction diode structures, such as MOS transistors, conduction modulated MOS
It is also found in transistors, Cyrisk, etc.

(Problem to be solved by the invention) As described above, in the conventional high-voltage planar semiconductor device,
There is a problem in that a plurality of mask processes are required to form a plurality of low impurity concentration layers having different impurity concentrations in order to increase the breakdown voltage.

The present invention has been made in view of the above points, and an object of the present invention is to provide a high-voltage planar semiconductor element and a method for manufacturing the same, which make it possible to obtain the same level of breakdown voltage as conventional ones through simple steps. .

[Structure of the Invention] (Means for Solving the Problems) The present invention has a pn junction structure in which a high impurity concentration layer of a second conductivity type is selectively formed on the surface of a high resistance semiconductor layer of a first conductivity type. A high breakdown voltage planar semiconductor element, comprising a first low impurity concentration layer of a second conductivity type diffused around and continuous with the high impurity concentration layer, the first low impurity concentration layer It is characterized by having a plurality of second low impurity concentration layers which are diffused around and continuous with the second low impurity concentration layers and have the same impurity concentration and partially overlap with each other.

The present invention also provides that when manufacturing such a semiconductor device, a first low impurity concentration layer and a plurality of second low impurity concentration layers are formed by impurity doping at one time using one mask having openings with different widths. It is characterized by being formed by an introduction process.

(Function) According to the present invention, the second low impurity concentration layer formed by multiple diffusions has the same impurity concentration as the first low impurity concentration layer individually, but when viewed as a whole, the second low impurity concentration layer has the same impurity concentration as the first low impurity concentration layer. The impurity concentration of the first low impurity concentration layer is lower than that of the first low impurity concentration layer. Therefore, unlike the conventional method, the first
．． This is equivalent to the case where the second low impurity concentration layer is continuously formed around the pn junction, and a high reverse breakdown voltage can be obtained. Moreover, according to the present invention, the first. The second low impurity concentration layer can be formed in a single impurity introduction step using one mask, which simplifies the manufacturing process.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the main part structure of a p + n junction diode of one embodiment. A p-type layer 2 having a high impurity concentration and serving as an anode is selectively formed on the surface of the n-type silicon layer 1. The diffusion depth of the p-type layer 2 is about 10 μm. A p-type layer 6 is formed as a first low impurity concentration layer around the p-type layer 2, and a second layer is formed around the p-type layer 6. Quadruple p as a low impurity concentration layer
- A mold layer 7 (7, to 75.) is formed. These p
The -type layers 6 and 7 were formed by one-time impurity diffusion using - masks. multiple p-type layers 7
are in a state where they partially overlap each other due to lateral diffusion of impurities.

The wafer surface on which the p-type layer 2 and p''''-type layers 6 and 7 are formed is covered with an oxide film 8, and a contact hole is opened in this to form an anode electrode 3 that contacts the p-type layer 2. ing. On the wafer surface further away from the p-type layer 7 by a predetermined distance, an n-type layer 9 and an electrode 10 in contact with the n-type layer 9 are formed to fix the surface potential. n-
A cathode electrode 5 is formed on the back surface of the type silicon layer 1 with an n÷ type layer 4 interposed therebetween.

FIG. 2 shows an enlarged view of a state in which adjacent four p-type layers 7 in FIG. 1 partially overlap. W in the figure is the mask width when forming the p-type layer 7. P-type impurities are introduced through mask openings formed at a distance of width W, and in the subsequent thermal diffusion process, a state is obtained in which the diffusion layers partially overlap each other within the range of width W due to lateral impurity diffusion. It will be done. In some cases, the overlapping range of the diffusion layers may be larger than the mask width W.

FIG. 3 shows the steps for forming the p-type layers 6 and 7 of the diode according to this embodiment. As shown in FIG. 3(a), an oxide film mask 11 is formed on the wafer surface on which the p medium-sized layer 2 is formed. The opening 12 of the oxide film mask 11 is the first
The plurality of openings 13 provided on the outside are for obtaining a p-type layer 7 which is a second low impurity concentration layer. It is.

P-type impurity ions are implanted using the oxide film mask 11 patterned in this manner. Thereafter, thermal diffusion is performed to obtain p-type layers 6 and 7 that partially overlap each other, as shown in FIG. 3(b).

Note that the diffusion after ion implantation of the p-type medium layer 2 can be performed simultaneously with the diffusion of the p-type layers 6 and 7.

By setting conditions so that the mask width of the region sandwiched by the openings 12 and 13 of the oxide film mask 11 and the diffusion depth due to thermal diffusion are approximately the same, the p-type layer 7 is formed by multiple diffusion. The region as a whole has a lower impurity concentration per unit area than the p-type layer 6, and is continuous as a diffusion layer.

FIG. 4 shows the results of numerical analysis of the relationship between the total amount of impurities per unit area and the withstand voltage as seen from the surfaces of the p-type layers 6 and 7 for the p-n junction diode according to this example. This data is obtained when the mask width for separating the p-type layer 6 and the plurality of p-type layers 7 from each other is set to 5 μm. Total amount of impurities is 1.87×1012/c
When the voltage exceeds II12, the withstand voltage drops rapidly. This is the point where the total amount of impurities becomes equal to that of the p medium layer 2, and if it exceeds this point, the effect of providing a low impurity concentration layer for the p medium layer 2 to alleviate electric field concentration is lost. p
- The total amount of impurities in type layers 6 and 7 is 1, 87 x 1
012/cm2, p medium layer 2 and n-type layer 1
A breakdown voltage of about 85% of that of the flat junction excluding the edge portions was obtained.

FIG. 5 shows the relationship between the width of the mask separating the p-type layers 6 and 7 and the withstand voltage of the diode of this example, also obtained by numerical analysis.

Points where the mask width/diffusion depth is slightly smaller than 1 (0,8~
A peak of breakdown voltage is observed at 1.0 point).

If the mask width is smaller than this, the overlapping of the multiple p-type layers 7 will be too large, and the impurity concentration per unit area will not be different from that of the p-type layer 6, and the impurity concentration will gradually decrease. Since the effect of forming the concentration layer around the high impurity concentration layer disappears, the withstand voltage suddenly decreases.

When the mask width/diffusion depth is 0.92, a breakdown voltage of about 85% of that of a flat junction can be obtained. When the mask width/diffusion depth is about 1.6 or more, the p-type layer 7 formed in multiple layers
will no longer overlap and be separated. For example, when the mask width/diffusion depth is 1.9, the breakdown voltage is reduced to about 72% of that of a flat junction.

FIG. 6 shows the main structure of a p+n junction diode according to another embodiment of the present invention. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. The difference from the embodiment shown in FIG.
Furthermore, a high resistance film 14 made of semi-insulating polycrystalline silicon or the like is disposed on the oxide film 8 on the wafer surface, spanning the outer n-type layer 1. One end of the high resistance film 14 is connected to the anode electrode 3, and the other end is connected to the electrode 10. As in the previous embodiment, the p-type layers 6 and 7 are -
It is formed by a single impurity introduction process using a single mask.

According to this embodiment, when a reverse bias is applied to the pn junction, a -like potential gradient is formed in the high resistance film 14, which prevents local concentration of the electric field. Higher reverse withstand voltage can be obtained compared to .

In the second embodiment, the second low impurity concentration layer p-
Although the mold layer 7 is formed in four layers, it may be formed in two or three layers, or may be formed in five or more layers.

Also, in the embodiment, a p+n junction diode was explained, but
The present invention can be applied to various high-voltage planar semiconductor elements such as MOS transistors including similar diode structures, SIRISK, and conduction modulation type MOS transistors.

[Effects of the Invention] As described above, according to the present invention, the impurity introduction process for forming a plurality of low impurity concentration layers for alleviating electric field concentration can be performed using a single mask, and the process can be performed in the same way as in the conventional method. A high breakdown voltage planar semiconductor element that can obtain a reverse breakdown voltage of about 100% can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main structure of a p + n junction diode according to an embodiment of the present invention, FIG. 2 is an enlarged diagram showing how the p-type layer 7 overlaps, and FIG. 3 (a) (b) is also p-
FIG. 4 is a diagram for explaining the formation process of the type layers 6 and 7, and shows the results obtained by numerical analysis of the relationship between the total amount of impurities in the p-type layers 6 and 7 and the breakdown voltage in the structure of Example 111. 5 is a diagram showing the results obtained by numerical analysis of the relationship between the mask width separating the p-type layer 7 and breakdown voltage, and FIG. 6 is a diagram showing the main points of a p+ n junction diode according to another embodiment of the present invention. FIG. 7 is a diagram showing the structure of a conventional high breakdown voltage p+n junction diode. 1...n-type silicon layer, 2...p medium-sized layer, 3...
・Anode electrode, 4...n medium layer, 5...cathode electrode, 6.p-type layer (first low impurity concentration layer), 7 (7
1 to 74)...p-type layer (second low impurity concentration layer),
8... Oxide film, 9... n medium layer, ]0... electrode,
11... Oxide film mask, 12.13... Opening, 14
...High resistance film. Applicant's agent Patent attorney Takehiko Suzue] 2

Claims (2)

[Claims] (1) A second conductivity type selectively applied to the surface of the high resistance semiconductor layer of the first conductivity type.
In a high-voltage planar semiconductor element having a pn junction structure in which a conductivity type high impurity concentration layer is formed, a second conductivity type first layer is diffused around and continuous with the high impurity concentration layer. a plurality of second low impurity concentration layers, which have a low impurity concentration layer and are diffused and formed around the first low impurity concentration layer so as to be continuous with the first low impurity concentration layer and to have the same impurity concentration and to partially overlap with each other; A high-voltage planar semiconductor device characterized by having a layer. (2) When manufacturing the high breakdown voltage planar semiconductor device according to claim 1, the first low impurity concentration layer and the plurality of second
1. A method for manufacturing a high voltage planar semiconductor device, characterized in that a low impurity concentration layer is formed in a single impurity introduction step using a single mask having openings of different widths.