JPH02189648A - Information processor - Google Patents

Abstract

PURPOSE:To more appropriately extract effective data for searching a fault by instructing the stop of processor operation by using the state change of a hardware signal as a trigger. CONSTITUTION:When a hardware signal 204 out of hardware signals 204 to 207 is turned to a logic '1' state specified by a command, a hardware signal state monitoring circuit 22 outputs an instruction for interrupting clock feeding to a clock feeding circuit 23. At the time of receiving the instruction, the circuit 23 immediately interrupts clock feeding to the processor 21 to stop the operation of the processor 21. When any one of the signals 204 to 207 is turned to logic '1' or '0' by an operator's command through a master device 10, the operation of the processor 21 is similarly stopped. Consequently, data indicating the operation state of the information processor can be easily extracted at a point of time close to the generation of a fault.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a data collection method for troubleshooting.

[Conventional technology]

Conventionally, in this type of information processing equipment, for the purpose of failure analysis, etc., the processor within the information processing equipment, which controls its operation, is stopped under certain conditions and data such as operation history is collected. In this case, when the firmware execution address matches the pre-specified address,
By interrupting the clock supply to the processor, we were able to stop the processor and collect data for failure analysis, such as the operating history at that point.

However, in the conventional information processing apparatus, as shown in FIG. 2, the execution address monitoring circuit 22' of the firmware instructs the clock supply circuit to suspend operation.

[Problem to be solved by the invention]

In the conventional information processing apparatus described above, for example, when a change in the state of a certain hardware signal is used as a trigger to instruct the processor 21 to stop, after the processor 21 detects the hardware signal, the firmware Since it is not possible to instruct the processor 21 to stop until the address of the microinstruction that indicates that the change in the state of the signal has been recognized is executed, there is a time lag between the time when the state of the hardware signal changes and the time when the processor actually stops. If this occurs and it is difficult to obtain accurate information, or if the firmware cannot recognize the change in the hardware signal, there is a problem in that it is not possible to use this as a trigger to stop the processor.

[Means to solve the problem]

The configuration of the information processing device of the present invention is such that the information processing device has a processor controlled by firmware and is capable of inputting a command via a host device and executing the command, in which the information processing device receives the information based on the instruction of the command. Hardware capable of selecting one of the hardware signals in a processing device, instructing a clock supply circuit for supplying an operating clock to the processor to suspend operation according to the state of the hardware signal, and stopping the processor. It is characterized by including a wear signal state monitoring circuit.

〔Example〕

Next, the present invention 10 will be explained with reference to the drawings.

) Figure 1 is a block diagram of an embodiment of the present invention. 1 in the diagram
0 is a host device, 20 is an information processing device according to the present invention, 21
is a processor; 22 is a hardware signal status monitoring circuit;
23 is a clock supply circuit. Here, as an example, a case will be described in which the instruction to stop the processor 21 is issued when the hardware signal 204 becomes the logic it 1 n state.

The hardware signal state monitoring circuit 22 selects the hardware signal 204 from among the hardware signals 204 to 207 in response to a command from the operator via the host device 10 and an instruction from the processor 21 via the control bus 201. monitors its status and detects its hardware signal 20.
4 becomes the logic "1" state specified by the command, it outputs an instruction to interrupt the clock supply to the clock supply circuit 23. Upon receiving this, the clock supply circuit 23 immediately stops supplying the clock to the processor 21. is interrupted to stop the operation of the processor 21.

Similarly, the operation of the processor 21 is stopped when any of the hardware signals 204 to 207 becomes logic ゛1''' or 0'° according to a command instruction from the operator via the host device 10. can be done.

〔Effect of the invention〕

As explained above, the present invention enables the instruction to stop the operation of the processor to be issued using a change in the state of a hardware signal as a trigger, making it easy to collect data on the operating state of an information processing device in the vicinity of the occurrence of a failure. This has the effect that effective data for troubleshooting can be collected more accurately.

Claims (1)

[Claims] In an information processing device that has a processor controlled by firmware and is capable of inputting a command via a host device and executing the command, one of the hardware signals in the information processing device is
a hardware signal state monitoring circuit capable of instructing a clock supply circuit for supplying an operating clock to the processor to suspend operation and stopping the processor according to the state of the hardware signal; Characteristic information processing device.