JPH02228759A - Digital data transfer equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital data transfer device that transfers digital data between systems having different clock frequencies.

[Prior Art] A digital data transfer device between systems having the same clock frequency but different synchronization has conventionally had a configuration as shown in FIG. In Figure 7, 10 is m
12 is a D-type flip-flop (hereinafter referred to as D-FF) that latches the input data of the input terminal 10; 14 is a shift register that can perform input and output asynchronously; 16 is a bit digital data input terminal; 18 is a digital data output terminal, 20.22 is a data transfer clock input terminal, and 24 is an inverter that inverts the clock at the clock input terminal 20.

The m-bit data sent from the transmitting side is input to the input terminal 10, and the transmitting side data transfer clock is input to the terminal 20. The D-FFI 2 latches the data at the input terminal 10 in accordance with this transmission side data transfer clock and outputs it to the shift register 14. Shift register 14 is connected to terminal 20
The data is taken in according to the clock of the terminal 22, and output according to the receiving side data transfer clock of the terminal 22. D-FF16 is terminal 2
The output data of the shift register 14 is latched in accordance with the receiving side data transfer clock No. 2, and outputted to the output terminal 18. In this way, data transfer between asynchronous systems takes place. It is assumed that the timing of data sent from the transmitting side changes with the rising edge of the data transfer clock.

[Problems to be Solved by the Invention] However, in the conventional example, data cannot be transferred between systems with different frequencies. For example, if the frequency of the data transfer clock on the transmitting side is higher than the frequency of the data transfer clock on the receiving side, the shift register 14 will overflow, and vice versa.
This is because it becomes empty.

Therefore, it is an object of the present invention to provide a digital data transfer device that can transfer data between systems with different frequencies.

[Means for solving the problem] A digital data transfer device according to the first invention of the present application includes:
A device for transferring digital data being transferred in synchronization with a first transfer clock using a second transfer clock having a frequency of 1/2 or less of the first transfer clock, the device a delay means for delaying the transfer clock of the digital data by the first transfer clock, a first register for transferring the digital data by the clock output from the delay means, and a first register for delaying the digital data by the second transfer clock. The second register transfers the output of the second register.

Further, the digital data transfer device according to the second invention of the present application transfers the digital data being transferred in synchronization with the first transfer clock to a second transfer having a frequency that is twice or more that of the first transfer clock. A device for transferring data using a clock, the device comprising: a delay means for delaying the first transfer clock by the second transfer clock; a first register for transferring input data using the first transfer clock; The second register transfers the output of the first register using the clock output from the delay means.

Furthermore, the digital data transfer device according to the third invention of the present application transfers the digital data being transferred in synchronization with the first transfer clock to a second transfer clock having a frequency different from that of the first transfer clock. a first delay in which the first transfer clock is delayed by a third clock having a frequency that is at least twice the higher frequency of the first and second transfer clocks; a first register that transfers input data using the first transfer clock; a second register that transfers the output of the first register using a tarlock output from the delay means; and a third clock. a second delay means for delaying the second transfer clock by the second delay means; a third register for transferring the output of the second register by the clock output from the second delay means; and a second delay means for delaying the second transfer clock. and a fourth register for transferring the output of the third register.

[Operation] According to the first invention, the relationship between the transfer timing of the first register and the transfer timing of the second register is such that a data transfer error does not occur in the second register. Therefore, it has become possible to reliably transfer the digital data being transferred in synchronization with the first transfer clock using the second transfer clock having a frequency of 172 or less than that of the first transfer clock.

Further, according to the second invention, the relationship between the transfer timing of the first register and the transfer timing of the second register is such that a data transfer error does not occur in the second register. Therefore, it has become possible to reliably transfer the digital data being transferred in synchronization with the first transfer clock using the second transfer clock having a frequency that is more than twice that of the first transfer clock.

Furthermore, according to the third invention, the relationship between the transfer timing of the first register and the transfer timing of the second register,
The relationship between the transfer timing of the second register and the transfer timing of the third register, and the relationship between the transfer timing of the third register and the transfer timing of the fourth register are different from those of the second, third, and fourth registers, respectively. The relationship is such that no data transfer error occurs. Therefore, it has become possible to reliably transfer the digital data being transferred in synchronization with the first transfer clock using the second transfer clock having a frequency different from that of the first transfer clock.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration block diagram of an embodiment of the present invention.

30 is an m-bit data input terminal, 32.34, 36
．． 38 is a D-FF that latches m-bit data; 4
0 is an output terminal for m-bit data, 42 is an input terminal for a transmitting side data transfer clock (first transfer clock in the second invention and third invention), and 44 is a receiving side data transfer clock (first transfer clock in the first invention). , 46 is an inverter for inverting the clock of the input terminal 42, 48.50 is a delay circuit, and 52 is a clock (second transfer lock) for controlling the delay circuit 48.50. This is an input terminal for the first transfer clock in the first invention and the second transfer clock in the second invention.

Note that the clock of the input terminal 52 has a frequency that is at least twice the higher of the frequency of the transmitting side data transfer clock (clock of the input terminal 42) and the frequency of the receiving side data transfer clock (clock of the input terminal 44). have.

The operation shown in FIG. 1 will be explained. The m-bit data sent from the transmitting side is input to the input terminal 30, and the transmitting side data transfer clock is input to the input terminal 42. Input terminal 42
The clock of D-FF is inverted by the inverter 46, and the clock of D-FF
32 is connected to the input terminal 30 according to the output 54 of the inverter 46.
The input data is latched and output to the D-FF 34 at the next stage. The output of the inverter 46 is delayed by a delay circuit 48,
It is applied to the D-FF 34 as a clock 56. D-F
F34 latches the output of D-FF32 according to this clock 56 and transfers it to D-FF36.

A receiving side data transfer clock is input to the input terminal 44, and the delay circuit 50 delays the receiving side data transfer clock based on the clock of the input terminal 52, and the D-FF3
6 as a clock 58. The D-FF 36 latches the output of the D-FF 34 in accordance with this clock 58 and transfers it to the D-FF 38. The D-FF 38 latches the output of the D-FF 36 according to the receiving side data transfer clock of the input terminal 44 and outputs it to the output terminal 40 .

A feature of this embodiment is that a delay circuit 56.60 is provided to set the clocks 54, 56, 58.60 of the D-FFs 32, 34, 36.38 in a predetermined relationship.

The relationship between these clocks 54, 56, 58, and 60 will be explained next. In Figure 2, 6
2 is m-bit data input terminal, 64.66 is D-F
F, 68 is an m-bit data output terminal, 70 is D-
Input terminal of clock CI to FF64, 72 is D-FF
This is the input terminal for the clock C2 to 66. In this circuit,
In order for the latch using clock C2 to operate normally, the third
In the timing chart shown in the figure, (Condition 1) t,,+t,,,≦It≦T
1, or in the timing chart of FIG. 4, (Condition 2) t, , +t, ≦'rat≦T.

It is necessary to satisfy one of the following. However, 1=12, T,
is the period of clock C1, T is the period of clock Cm, t
, 4 is the propagation delay time of D-FF64, 66, and t mu is D-FF64. 66 data set-up times. Condition 1 is used when the period T of the clock C1 is known, and Condition 2 is used when the period T of the clock C2 is known.

The conditions according to Condition 1 or Condition 2 are equivalent to the following conditions. That is to say.

Condition 3 can be used whether the cycles of clocks CI and C* are known or unknown.

From the above, it can be understood that the time difference between the clocks of the cascade-connected D-FFs only needs to satisfy any one of conditions 1 to 3. The delay circuits 48 and 50 that meet these conditions are each composed of 1-bit D-FFs, and as described above, the frequency of the clock of these D-FFs is the same as that of the transmitting side data transfer clock and the receiving side data transfer clock. It is sufficient that the frequency is at least twice as high as the higher frequency of the side data transfer clock. However, this is the case where the duty is assumed to be 50%, and is the minimum frequency for delaying the human clock without thinning it.

When the duty of the data transfer clock deviates from 50%, an even higher frequency is required.

In FIG. 1, if the period of the transmitting side data transfer clock at the terminal 42 is T, the period of the receiving side data transfer clock at the terminal 44 is T5, and the period of the clock at the terminal 52 is T6, then the delay of the clock 56 with respect to the clock 54 is time τ8
, delay time τ2 of clock 58 with respect to clock 56,
and the delay time τ of the clock 60 with respect to the clock 58
, becomes as follows.

1,,+1,,≦τ1<T−+t,,+
t, uT* = nT, (n=0.1, 2. ・-
)τ @>Tb Tt tau t
,.

τ, ≦T> t-t, d, where T1 ≦'r, /2. Tb/2. Also, ”, +t, and u are generally very small,
1,,+1,,≦T,/2. Therefore, t ea + t--≦τ, <Tl r * = n T , (n = 0.1, 2
．．・−)t,,+tsv≦τ,≦T.

becomes. These formulas satisfy the conditions 1 to 3 described above and can reliably transfer m-bit digital data.

FIG. 5 shows a block diagram of a specific example of the configuration of the delay circuit 48. 74 is a D-F that operates according to the clock of the terminal 52.
F, 76 is a delay element with a fixed delay time t. In this case, τ,≧1,,+1□+t.

τ+　<T, +tp, +t, 11+t.

r 2 = n Ta t g (n = 0
．． 1,2s·1τs>Tb Tt−, tpa τ, ≦Tb tt.

becomes. Here, if tp≦Tc/2, the above formula satisfies any of the conditions 1 to 3 described above.

Although the above-mentioned embodiment shows an embodiment corresponding to all of the first, second, and third inventions of the present application, for example, the structure of the first and second inventions alone can be similarly configured.

FIG. 6 shows a configuration block diagram of an embodiment of the first invention of the present application. The same components as in FIG. 1 are given the same reference numerals.

As can be seen from a comparison with FIG. 1, FIG. 6 has a configuration in which the D-FFs 32, 34, clock input terminal 42, inverter 46, and delay circuit 48 of FIG. 1 are omitted.

This configuration is applicable when digital data from the transmitting side is input to the input terminal 30 in synchronization with a clock obtained by dividing the clock at the terminal 52 (first transfer clock); The frequency of the clock is
The frequency may be at least twice the frequency of the data transfer clock on the receiving side.

Similarly, the embodiment of the second invention of the present application is the D-FF32 shown in FIG.
．． 34, an inverter 46, and a delay circuit 48.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, digital data transfer between systems having different clock frequencies can be realized with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an embodiment of the present invention, FIG. 2 is a block diagram for explaining the operating principle of FIG. 1, FIGS. 3 and 4 are timing charts for FIG. 2, FIG. 5 is a configuration example of the delay circuit 48 shown in FIG. 1, FIG. 6 is a configuration block diagram of an embodiment of the first invention of the present application, and FIG. 7 is a configuration block diagram of a conventional example. 30: Data input terminal 32, 34, 36.38 = D-type flip-flop 40: Data output terminal 42.44.
52 + clock input terminal 46: Inverter 48,5
0: Delay circuit

Claims (3)

[Claims] (1) A device for transferring digital data being transferred in synchronization with a first transfer clock using a second transfer clock having a frequency that is 1/2 or less of the first transfer clock, a delay means for delaying the second transfer clock by the first transfer clock; a first register for transferring the digital data by the clock output from the delay means; A digital data transfer device comprising: a second register that transfers the output of the first register; (2) A device for transferring digital data being transferred in synchronization with a first transfer clock using a second transfer clock having a frequency that is twice or more that of the first transfer clock, the first transfer clock to the second
a first register that transfers input data using the first transfer clock; and a first register that transfers input data using the first transfer clock;
and a second register for transferring the output of the register. (3) A device for transferring digital data being transferred in synchronization with a first transfer clock using a second transfer clock having a frequency different from that of the first transfer clock, and a first delay means for delaying the first transfer clock by a third clock having a frequency that is at least twice as high as the higher frequency of the second transfer clock; a first register to transfer, a second register to transfer the output of the first register by a clock output from the delay means, and a second register to delay the second transfer clock by the third clock. a delay means; a third register that transfers the output of the second register according to the clock output from the second delay means; and a fourth register that transfers the output of the third register according to the second transfer clock. A digital data transfer device comprising a register.