JPH0225516B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voice synthesis method for synthesizing voice data and outputting a voice signal, and particularly to a method for starting synthesis of voice data.

As a voice synthesis method, PCM (Pulse
codemodulation), DPCM (differential PCM)
PARCOR (partial
autoecorrelation) method, LPC (liner
pedictive coding) method, and even LSP (line
spectrumpair (line spectrum pair) method, etc. are known. Among these, the LSP method encodes the characteristics of the frequency spectrum using frequency domain parameters, and is designed to improve sound quality and reduce the amount of information compared to the linear predictive coding (LPC) method. This method has a higher degree of data compression than the encoded waveform encoding method.

Speech synthesis using the parameter encoding method, for example, uses one set of audio data (for example, 6
bytes) according to a predetermined procedure, and the interpolated output for each sample period is added as a coefficient of a digital filter using linear interpolation, etc., and the pulse train or white noise from the sound source section is added to the digital filter as a driving sound source to obtain a speech synthesis output. It is something. Normally, the audio data of the next frame is read during the processing of a certain frame, but when the system or speech synthesis circuit is started for the first time, there are shift registers, arithmetic circuits, etc. inside the speech synthesis circuit. The states of the flip-flop circuits included in these circuits are undefined. Therefore, it is necessary to initialize the arithmetic circuits, etc. (clear the flip-flops) before starting the speech synthesis operation.

In order to eliminate the undefined state of the circuit described above, the present invention initializes the speech synthesis circuit within a predetermined time for speech synthesis, receives activation for starting speech synthesis, and then actually performs speech synthesis. The purpose is to shorten the time required to start and stably perform voice synthesis.

In order to achieve the above object, the present invention provides a speech synthesis device using a parameter encoding method that reads speech data and converts the speech data into parameters such as conversion, interpolation, calculation, etc. to synthesize speech. , the voice synthesis circuit is initialized for a predetermined period of time by an external activation signal, and when the voice data is received before the initialization is completed, the voice synthesis operation is started upon completion of the initialization. , when the reception of the voice data is performed after the completion of the initial settings, the voice synthesis operation is started upon completion of the reception of the voice data, and the voice synthesis operation immediately after the start of the voice synthesis operation is voice data conversion. The present invention is characterized in that the obtained result is input to a digital filter section and subjected to arithmetic processing without interpolation processing.

The present invention will be described in detail below based on Examples.

Figure 1 is a block diagram of a system that performs speech synthesis under the control of a microprocessor.
is a microprocessor, 2 is a memory that stores audio data, 3 is a speech synthesis circuit, 4 is a crystal oscillator for oscillating the original signal for timing generation, etc., 5 is a digital-to-analog converter, 6 is a low-pass filter,
7 is an amplifier, 8 and 10 are speakers, and 9 is a transformer.

Based on the address signal from the microprocessor 1, audio data is read from the memory 2 and applied to the speech synthesis circuit 3, and control information from the microprocessor 1 controls the start, stop, and frame period of speech synthesis in the speech synthesis circuit 3. The selection, etc. of
will be sent to. When the audio output of the audio synthesis circuit 3 is a digital serial output, it is converted into an analog audio signal by a digital-to-analog converter 5, and is applied to an amplifier 7 via a low-pass filter 6, and a speaker 8 is driven by the amplified output. Furthermore, since the voice synthesis circuit 3 has a built-in simple digital-to-analog converter, the speaker 10 can also be driven via the transformer 9. The audio quality in this case is somewhat low because it is converted into an analog audio signal by a simple digital-to-analog converter.

Figure 2 is a block diagram of the speech synthesis circuit.
Reference numeral 11 denotes a data buffer stack consisting of a group of shift registers in which audio data D ₀ to D ₇ are set by a signal DL and held until the audio data is converted.
2 is the interface section, 13 is the start and stop signal
ST, repeat signal RPT that stops interpolation and specifies repeat synthesis operation of the same data, frame period setting signals T ₀ , T ₁ , variable/fixed frame length mode specification signal MODE, specifies stop of voice synthesis by information in the voice data A control register 14 is used to set control signals such as a stop bit enable signal SBE, etc., and a control register 14 is a control register that sets control signals such as a stop bit enable signal SBE.
A status register that outputs a display signal during speech synthesis using a signal SE; 15 is a speech converter; 16
17 is a conversion unit consisting of a read-only memory (ROM) or the like that converts audio data into film coefficients; 17 is an interpolation unit that interpolates and outputs filter coefficients added every frame period; 18 is a sound source unit; 2 is a digital filter section, 20 is a simple digital-to-analog converter, and 21 is a control section that generates timing signals and controls each section.
This is the case when it is made into an integrated circuit. The symbols shown at each terminal represent signals, V _DD , V _SS , and V _SA are power supply voltages, SOUT is, for example, a 16-bit serial digital audio output signal, and POUT and NOUT are, for example, 8-bit simple digital-to-analog converter 20. analog audio output signal converted to analog signal,
XOUT is the basic clock for internal logic operations,
WSYN is the SOUT synchronization signal, MR is the internal flip-flop, counter reset signal, CKST
is a control signal for the crystal oscillator circuit, CLK and XTAL are crystal resonator connection terminals, and FP is a frame pulse output terminal indicating the sampling period at the beginning of each frame.

In the case of the LSP method, the audio data includes, for example, a 1-bit start bit, 7-bit pitch cycle data, 2-bit frame length designation bits, and 6-bit start bit.
A set of 6 bytes consisting of bit amplitude data and 8 LSP parameters of 4 bits each.
For example, the frame length can be specified as 5, 10, 20, or 40 ms.

Such audio data is read from the memory into the data buffer stack 11, set by a signal (data load pulse), and converted into the converter 16.
The filter coefficients are converted into filter coefficients using the LSP parameters and amplitude data, and sent to the interpolation unit 17. The interpolation section 17 performs linear interpolation for each sample period and sends filter coefficients to the digital filter section 19. Further, the sound source section 18 generates a pulse train according to the pitch period data in the audio data, and applies it to the digital filter section 19.

The digital filter unit 19 includes an addition/subtraction circuit, a multiplication circuit, etc., and operates as a voice synthesis filter by calculating the pulse train from the sound source unit 18 and the filter coefficients from the interpolation unit 17, and generates, for example, a 16-bit serial digital audio signal. Output.

FIG. 3 is a block diagram of the main parts of the embodiment of the present invention, in which the same reference numerals as in FIG. Information holding register, 33 is a driving sound source generating section, 34 is a difference value register, 35 is a 1/2n circuit, 36 is an interpolation value register, 37, 41
is an adder circuit, 38 and 43 are inhibit gates,
39 and 42 are AND gates, and 40, 44, and 45 are OR gates.

The audio data D ₀ to _{D 7} read from the memory are set in the data buffer stack 11 by the data load pulse DL. This audio data is read out by the conversion read timing pulse t ₁ , and the amplitude data and LSP parameters are sent to the conversion section 16 and the pitch period data to the holding register 32 of the sound source section 18 . The contents of the holding register 32 are updated to the driving sound source generating circuit 33 by the bit cycle data update timing pulse _t2 . Drive sound source generation circuit 3
3 outputs a pulse train (periodic pulses or pulses equivalent to white noise) according to the pitch synchronization data of the contents of the register 32, and is applied to the digital filter section 19.

The conversion output of the conversion unit 16 is normally (during speech synthesis)
is added to the adder circuit 37 of the interpolation unit 17, the difference with the filter coefficient of the previous frame is output, and set in the difference value register 34 by the difference value calculation timing pulse _t3 , and the 1/2n circuit 35 outputs the difference with the filter coefficient of the previous frame. It is divided into several increments. In other words, the difference between the coefficients input from the converter 16 and the coefficients of the previous frame is determined for each frame period by the adder circuit 37, and this difference is removed by the 1/2n circuit according to the number of samples in one frame. Then, a value for each sample is obtained, and this value is added to the contents of the interpolation value register 36 in an adder circuit 41, and a filter coefficient for each sample is output to the digital filter section 19. At this time, the output of the startup control circuit 31 is "0", the gate 42 is closed, and the gate 4
3 is open.

On the other hand, the point at which speech synthesis starts, that is, the start signal
When ST changes from "0" to "1", in the first frame pulse EP, the conversion result output from the conversion unit 16 is not interpolated and is sent to the gate 4.
2, the signal is sent to the digital filter 19 as it is. The startup control circuit 31 controls gate control (42, 42,
43 gates). Start-up control circuit 3
1, it is determined whether or not the start signal ST is set based on the timing pulse _t4 , and the frame pulse
Determine the initial setting time from FP and sampling clock D and output "0" to each circuit. is a control register load signal that sets the activation signal, and MR is a reset signal that resets the flip-flops of the speech synthesis circuit from the outside.

FIG. 4 is a block diagram of the main parts of the start-up control circuit 31, in which FF ₁ is a holding type flip-flop, FF ₂ ,
FF ₃ and FF ₉ are delay flip-flops operated by the basic clock t ₄ '; FF ₃ , FF ₄ , FF ₅ , and FF ₇
is a delay type flip-flop operated by the sample clock D, _FF6 is a delay type flip-flop operated by the basic clock _t4 , _FF10 is an asynchronous flip-flop, 51, 54, 60 are inverters, 52, 55, 56, 58. , 59 is an AND gate, 53 is an OR gate, 57 is a NAND gate, 61 is an inhibit gate, and RDF is a data ready signal indicating that the audio data generated within the interface section is complete.

When the start signal ST is set and held at _FF1 by the control register load signal CRL, the basic clock pulses t4' and _{t4 '} ' are The gate 56 is opened until FF ₃ , FF ₄ , and FF ₅ are sequentially driven by the sample clock D from the time when the initial setting signal INI is input to the control section 2.
1 and FF ₁₀ INI. Since the startup signal ST is sent to FF ₅ at the second sample clock, the initial setting signal INI is output for 2 to 3 samples. When the audio data is set after outputting the initialization signal INI, the data ready signal RDF is set and the gates 59 and 58 are opened, thereby sending a start signal to the digital filter section 19, control section, etc. to start speech synthesis. This activation signal ST causes the control unit to generate a frame pulse FP, which is input to the flip-flop FF ₉ and also to the gate 61.
Since FF ₁₀ is set by the initial setting signal INI, the gate 42 of the interpolation section in FIG. 3 is kept open until the output of the gate 61 becomes "1" at the trailing edge of the frame pulse FP and resets the flip-flop FF ₁₀ . It turns out. flipflop FF ₁₀
When is reset by the reset signal R, the gate 43 is opened and interpolation calculation begins.
Since the difference value is “0” in the frame,
As a result, the conversion result is sent to the digital filter section 19 for each sample.

If the audio data has been input to the data buffer stack before the activation signal ST is input, the data ready signal RDF has been set, and the initialization signal INI has been completed (for example, changing from "1" to "0"). )
At the same time, generate the first frame pulse,
The conversion result is sent to the interpolation section and also to the digital filter.

In this way, the initial setting signal is generated for a period of at least two sampling pulses after the flip-flop FF is set to ₁ (for example, "1"), and if data reception is completed by the time the initial setting is completed, the initial setting is completed at the same time. Start voice synthesis for the first frame,
If data reception is not completed by the time the initial settings are completed, the first frame can be started at the time of the first sampling pulse after data reception is completed.

FIG. 5 shows a time chart when data is received before the speech synthesis circuit is activated. data request signal
REQ goes low when data is read from the data buffer stack for each frame pulse, and goes high when data DATA is requested and the data is stored in the data buffer stack.
The failure signal becomes a low level unless data is set during a data request after the activation signal ST is input. (Fig. 5 shows an example of a state where the high level is always H.) Here, a is a state in which synthesis is stopped, and data is set before the start signal is input, so
The internal initialization b is performed in a short time until the first frame pulse is generated, and the conversion c of the first data #1, the digital filter operation d based on the conversion result of the first data #1, and the conversion of the second data #2 are performed. and #1
→ Difference calculation of #2 e, interpolation of data #1 → #2 and digital filter operation f, conversion of data #3 and difference calculation of #2 → #3 g, data #2 →
Speech synthesis is performed in the order of #3 interpolation and digital filter operation h.

FIG. 6 shows a time chart when data is received after the voice synthesis circuit is activated.

The symbols shown here have the same meanings as those in Fig. 5, but the difference from Fig. 5 is that the audio data is stored in the data buffer stack after the activation signal ST is set. It is in a state of

The fault signal goes low until the data is stored, and goes high together with the data request signal after the data is set. The first speech synthesis starts after the start signal ST is set.
As explained in the figure, when data #1 is stored after initialization for 2 to 3 sampling periods, the first frame pulse is generated and speech synthesis is started. Speech synthesis using this first frame pulse is performed by outputting the conversion result of data #1 to a digital filter and performing filter operation d, as in FIG. Perform operations f and h.

As explained above, according to the present invention, the voice data converted in the first frame at the start of voice synthesis is sent to the digital filter section without being subjected to interpolation, etc. Since there is no interpolation, there is no abnormal signal generation, and after the start signal is input, the initial setting is performed for 2 to 3 sample cycles, and if the data is set in advance, a frame pulse is immediately generated, and the data is If it is set later, the first frame pulse is generated from the first sampling pulse after the data reception is completed, so the voice synthesis start operation can be performed extremely quickly, and there is no variation in the start time, resulting in stable voice synthesis. Initiation can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system that performs speech synthesis under the control of a microprocessor, FIG. 2 is a block diagram of a speech synthesis circuit, FIG. 3 is a block diagram of main parts of an embodiment of the present invention, and FIG. The figure is a block diagram of the main part of the start-up control circuit according to the embodiment of the present invention.
6 are time charts for explaining the speech synthesis start method of the present invention. FIG. 5 shows a case where data is received before starting the speech synthesis circuit, and FIG. 6 shows a case where data is received after starting the speech synthesis circuit. This is the case when it is received. _D0 to _D7 ; Audio data, 11; Data buffer stack, 16; Conversion section, 18; Sound source section, 17;
Interpolation unit, 19; Digital filter, 31; Start-up control circuit, DL: Data load pulse, ST: Start-up signal, FP: Frame pulse, D: Sampling clock, _t1 to _t4 : Basic clock.

Claims (1)

[Scope of Claims] 1. A speech synthesis device using a parameter encoding method that reads speech data and synthesizes speech by parameterizing the features of the speech through processing such as conversion, interpolation, and calculation of the speech data, comprising: a speech synthesis circuit; initializes the speech synthesis circuit for a predetermined period of time using a startup signal externally activated, and when the audio data is received before the completion of the initialization, the speech synthesis circuit is started upon completion of the initialization. . A voice synthesis start method, characterized in that when the voice data is received after the initial setting is completed, the voice synthesis operation is started upon completion of the voice data reception. 2. In the statement of claim 1, the voice synthesis operation immediately after the start of the voice synthesis operation is characterized in that the result of converting the voice data is input to a digital filter section without interpolation processing, and arithmetic processing is performed. Speech synthesis starting method.