JPH02273941A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the decrease of yield, and improve the reproducibility of size by isotropically etching a wiring pattern. CONSTITUTION:On a semiconductor substrate 1, a lower part film 5 is formed, on which a wiring pattern 8 is formed, and said pattern is isotropically etched. An upper part mask 9 is formed on the whole surface; the etched wiring pattern 8 is eliminated; by using the left upper film 9 is a mask, the lower part film 5 is etched, thereby exposing the substrate surface. A metal film is formed on the whole surface, and the lower part film 5 is eliminated. Thereby, forming a wiring and an electrode with fine size is enabled without using expensive equipments, and yield and reproducibility can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a gate pole of an FET or HFMT.

(b) Conventional technology Conventionally, field effect transistors, such as GaAs! II
The ESFET consists of a semi-insulating GaAs substrate, an n-type active layer formed on this substrate, an ohmic contact source electrode and a drain electrode formed on this active layer, and the source tpi and drain 1 connected between the electrodes. It consists of a Schottky contact gate 1jL pole formed on the active layer.

By the way, the low noise of the GaAs MES FET mentioned above,
In order to achieve high gain, it is necessary to shorten the gate length, and this requires forming a quarter-micron gate pattern, and electron beam direct writing technology is often used. However, using this method to shorten the gate length requires expensive equipment, and it is difficult to improve yield and reliability, so it is not necessarily the best method from a practical standpoint. I can't say that.

For this reason, methods for forming automicron gate electrodes using light exposure are being actively developed, including methods using a two-layer process and an image reversal method (B-
D. Cantos and R-D-Remba, J.
Electrochem, Soc, May (198
8) (see P13] 1-1312)).

In this method, first, a first resist that can be flattened is applied onto a substrate on which source and drain electrodes are formed.

Next, a positive second resist is applied to the first resist surface, and a 0.65 μm gate photomask is applied to the resist.
The second resist is exposed to light, and a gate resist pattern of 0.65 μm with excellent contrast is formed using an image inversion method. Further, by wet developing the second resist, the gate resist pattern is shortened to 0.25 μm. After that, A on the entire surface
After 1000 I deposition steps, unnecessary AI is removed together with the second resist to form an AI agate mask with a thickness of 0.degree. 25 .mu.m. Next, use the AI agate mask as a mask,
0. After selectively removing the first resist using plasma, etching the active layer between the source and drain electrodes;
Form a recess. Finally, a gate electrode of 0.25 μm made of AI is formed in the recess.

(c) Problems to be Solved by the Invention In the conventional technology, it is necessary to carry out excessive wet development in order to shorten the gate resist pattern, which causes the resist to swell and easily peels off the gate resist pattern. Decrease yield. In addition, in order to control the dimensions of the gate resist pattern, advanced techniques such as strict temperature control techniques for the developer and a stirring method are required, resulting in a problem of poor dimensional reproducibility.

(D) Means for Solving the Problems The present invention comprises a process of forming a lower film on a semiconductor substrate, a process of forming a wiring pattern on this lower film, and a process of isotropically etching this wiring pattern. a step of forming an upper film on the entire surface; a step of removing the etched wiring pattern; a step of etching the lower film using the remaining upper film as a mask to expose the surface of the substrate; A method for manufacturing a semiconductor device, comprising the steps of forming a film and removing the lower film.

(E) Function In the present invention, by etching the wiring pattern isometrically, the dimensions of the wiring pattern can be shortened without changing the shape of the wiring pattern.

(f) Example An example in which the method of the present invention is applied to the production of a GaAs MES FET will be described with reference to FIGS. 1(a) to (g).

n on the semi-insulating GaAs substrate (1) by vapor phase growth method etc.
Grow the physical body layer (2) by 3000 people. Subsequently, a photoresist having openings is formed on the n-type moving body layer (2) at the locations where the ohmic electrodes are to be formed, and using the photoresist as a mask, ohmic electrode metals such as Au-Ge/N i / Au are formed. A source electrode (3) and a drain electrode (4) are formed by a 2,000-person evaporation lift-off method (FIG. 1(a)).

Next, a first resist (lower film) (SAL-110-PLI (manufactured by Sibley)) whose upper surface is flattened is applied on the n-type moving body layer (2), the source electrode (3), and the drain electrode (4).
5) Form. Furthermore, a negative second resist (AZ5200E (manufactured by Hoechst)) (6) with excellent resolution and contrast is formed on the first resist (5), and a photomask (7) ( Gate length 0.4
μm) to expose the second resist (6) (first
Figure (b)).

Next, the second resist (6) is developed and the gate length is 0.
．． 4μm gate electrode pattern (wiring pattern) (8)
After forming the first resist (5) and the second resist (6), the first resist (5) and the second resist (6) are isotropically etched with O plasma,
The gate length of the gate electrode pattern (8) is shortened to 0.2 μm. However, 0. The plasma conditions are gas flow rate 0, 4
05CCM, etching pressure 200 mTorr, output 500Th, etching time 6 minutes (Fig. 1(c))
, Figure 1(d)). Then, Ti (upper film) (9) was added to 1
After 2,000 people evaporation, apply a second resist with acetone (6)
and unnecessary Ti(9) is removed (FIG. 1(e)).

Subsequently, using the remaining Ti (9) as a mask, anisotropic etching 03 is carried out to selectively remove the first resist (5) and form an opening (10). ) to form a recessed portion (11) (FIG. 1(f)).

Finally, 500 Ti, 500 Pt, 3000 Au
After depositing the gate electrode metal (metal film), the first resist (6) is removed using a stripping agent (Microposit Remover 1165 (manufactured by Shipley)) to form a gate electrode with a gate length of 0.2 μm. (12) (Fig. 1 (
g)).

(G) Effects of the Invention As is clear from the above description, the present invention enables the formation of fine-sized wiring and electrodes without using expensive equipment, using conventional light exposure methods with good yield and reproducibility. This is made possible using dry etching technology.

[Brief explanation of drawings]

FIGS. 1(a) to 1(g) are process explanatory diagrams for explaining one embodiment of the present invention. (1) Semi-insulating GaAs substrate, (2) Active layer, (3) Source electrode, (4) Drain electrode, (5) First resist , (6)...second
Resist, (7)...7 otomask, (8)...
Gate with polar pattern, (9)...Ti mask, (10
)・・・Cleaning part, (11)...Recess part, (12)・
...Gate electrode.

Claims (1)

[Claims] (1) A step of forming a lower film on a semiconductor substrate, a step of forming a wiring pattern on this lower film, a step of isotropically etching this wiring pattern, and a step of forming an upper film on the entire surface. , a step of removing the etched wiring pattern, a step of etching the lower film using the remaining upper film as a mask to expose the substrate surface, a step of forming a metal film on the entire surface, and a step of removing the lower film. A method of manufacturing a semiconductor device, comprising the step of removing.