JPH02284520A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To always attain an operation at the optimum processing speed by changing a clock frequency-dividing value in accordance with the instruction of a program at the time of a normal action and selecting an appropriate value from plural initial frequency-dividing values at the time of an action independent of the program of reset, etc. CONSTITUTION:A frequency-dividing circuit 2 divides a source clock which is generated with a source clock generation circuit 1 at a set frequency-dividing rate and gives it to the other circuit 3 of a program storage circuit which is incorporated in a semiconductor integrated circuit. A reset signal input pin 8 inputs a reset signal from outside and gives it to a frequency-dividing register 4. A selector 7 selects one of four initial frequency-dividing value setting means 61, 62, 63 and 64 constituted of digital switches, code generation circuits, etc., in accordance with selection signals (SEL 1, 2 and 3) inputted from outside through initial frequency-dividing value selection pins 91, 92 and 93. Then, one of the initial frequency-dividing values A, B, C and D is stored in the frequency- dividing value register 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that divides a supplied clock pulse by a predetermined ratio to obtain a basic clock for operation.

[Conventional technology]

FIG. 3 is a block diagram showing the structure of a semiconductor integrated circuit incorporating a programmable clock frequency divider proposed by the present applicant in Japanese Patent Application No. 61-278330. In the figure, 1 is an original clock generation circuit, and a frequency division circuit 2 divides the original clock generated by the original clock generation circuit 1 by a division ratio set by a division value setting means 5, which will be described later. Other circuits such as program storage circuits built into semiconductor integrated circuits 3
give to

The frequency division value register 4 stores the frequency division value given to the frequency division circuit 2, and the frequency division value setting means 5 divides the frequency division value into the frequency division value register 4 according to the program written in the built-in program storage circuit or the program read from the outside. Set the frequency value. Reset signal input pin 8 accepts an external signal (RES).
[! T) is input and given to the frequency division value register 4, and the frequency division value stored in the frequency division value register 4 is reset. The initial frequency division value setting means 6 outputs the initial frequency division value to the frequency division value register 4 at the time of reset.

In a conventional semiconductor integrated circuit with a built-in clock frequency divider configured as described above, when executing a built-in program or an externally given program, the required frequency division value is written at the beginning of these programs, and the program is executed. Obtain the basic clock used for execution.

That is, if you want to operate faster, write an instruction to reduce the frequency division value, and if you want to operate at lower speed, write an instruction to increase the frequency division value at the beginning of the program. In this way, by setting the processing speed to the optimum speed according to the processing content of the program, it is possible to reduce power consumption due to swifting in, for example, a CMO5 semiconductor integrated circuit, without reducing the overall processing speed. can.

On the other hand, when the signal "1" is input from the reset signal input pin 8 or at the time of cent, the frequency division value stored in the frequency division value register 4 is reset, and the frequency division value stored in the frequency division value register 4 is transferred from the initial frequency division value setting means 6 to the frequency division value register 4. An initial frequency division value is given. Frequency divider circuit 2
divides the original clock generated by the original clock generation circuit 1 according to the initial frequency division value stored in the frequency division value register 4, and outputs this as a basic clock to the other circuits 3 and the frequency division value setting means 5. do.

[Problem to be solved by the invention]

Therefore, in a microcomputer equipped with the conventional semiconductor integrated circuit as described above, when performing a test that is not based on a program, such as reading from an internal ROM, at reset, the frequency division ratio remains fixed and the operation It was impossible to change the value to an appropriate value.

The present invention has been made to solve such problems, and by making it possible to set the frequency division ratio according to an externally applied signal during non-programmed operation, The purpose of the present invention is to provide a semiconductor integrated circuit that can obtain an optimal basic clock even in the case of a semiconductor device.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a frequency division ratio setting means that can set a plurality of frequency division ratios, and a frequency division ratio that the frequency division ratio setting means should set according to a signal etc. input from an input terminal. It is characterized by comprising means.

[Effect]

The semiconductor integrated circuit of the present invention stores a plurality of frequency division ratios, and during normal operation according to a program, divides the original clock according to the frequency division ratio set by the program and uses it as a basic clock for operation. During operation not based on a program, the frequency division ratio is selected according to the selection signal input from the input terminal, the original clock is divided according to the selected frequency division ratio, and this is used as the basic clock for operation not based on a program. circuit, and operates at optimal processing speed even when not programmed.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit according to the present invention. 1 in the figure is the original clock generation circuit,
The frequency dividing circuit 2 divides the original clock generated by the original clock generating circuit 1 by a set frequency division ratio and supplies the divided clock to other circuits 3 such as a program storage circuit built in the semiconductor integrated circuit. The division value register 4 stores the division value given to the frequency division circuit 2, and the division value setting means 5 divides the frequency into the division value register 4 according to the program written in the built-in program storage circuit or the program read from the outside. Set the value. Reset signal input pin 8 accepts an external signal (
R [! 5ET) and gives it to the frequency division value register 4.

Selector 7 is externally connected to initial frequency division value select pins 91, 9.
2.93 input selection signal (SEL 1, 2
．． 3), four initial frequency division value setting means 61, 62 consisting of, for example, a digital switch, a code generation circuit, etc.
, 63.64, and set the initial frequency division value (A).
, (B), (C), or (D) is stored in the frequency division value register 4.

The operation of the semiconductor integrated circuit having the above-described configuration at the time of installation will be explained. Note that the operation during normal operation depending on the program is similar to the operation of the conventional circuit described above.

At the time of reset when "1" is input from the reset signal input pin 8, the frequency division value stored in the frequency division value register 4 is reset, and the initial frequency division value selected by the selector 7 is stored in the frequency division value register 4. be done.

The selector 7 has initial frequency division value select pins 91, 92.9.
3 is "0.0.0", the initial frequency division value setting means 61 is selected to set the initial frequency division value (A) to "0.0.0".
When the value is 1°0.0, the initial frequency division value setting means 62 is selected to set the initial frequency division value (B), and when the value is "0, 1.0", the initial frequency division value setting means 63 is selected and the initial frequency division value (B) is set. The circumference value (C) is “0,0
．． 1'', the initial frequency division value setting means 64 is selected and the initial frequency division value (D) is stored in the frequency division value register 4.

The frequency dividing circuit 2 divides the original clock generated by the original clock generating circuit 1 according to the initial frequency division value stored in the frequency division value register 4, and uses this at the time of reset, for example, when reading data from a ROM. It is output to other circuits 3 and frequency division value setting means 5 as a basic clock.

After the reset is canceled by inputting 0'' from the reset signal input pin 8, only the frequency division value setting means 5 sets the frequency division value in the frequency division value register 4. At that time, the frequency division value written in the built-in circuit When a frequency division ratio change instruction of a program or a program read from an external device is executed, the frequency division value setting means 5 sets a frequency division value according to the program instruction in the frequency division value register 4, and the frequency division circuit 2 The frequency of the original clock is divided according to the frequency division ratio stored in the frequency division value register 4.

In the above embodiment, three initial frequency division value selection pins are provided, but if there are four selection targets, two initial frequency division value selection pins are sufficient as shown in FIG.

That is, the selector 7 selects the initial frequency division value select pin 91.9.
2, the initial frequency division value setting means 61 is selected and the initial frequency division value (^) is set to "0.
When the value is "1", the initial frequency division value setting means 62 is selected to set the initial frequency division value (B), and when the value is "1, 0", the initial frequency division value setting means 63 is selected.
When it is "1.1", the initial frequency division value setting means 64 is selected and the initial frequency division value (D) is stored in the frequency division value register 4.

〔Effect of the invention〕

The semiconductor integrated circuit of the present invention changes the clock frequency division value according to the instructions of the program during normal operation when executing a program written in the built-in circuit or a program read from the outside, and a circuit that does not depend on the program after reset. During operations such as tests, the basic clock for operation can be set arbitrarily by selecting an appropriate value from multiple initial frequency division values, and for example, reading from internal ROM can be performed at high speed, without depending on the program. Even during operation, it has the excellent effect of operating at optimal processing speed.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the structure of a semiconductor integrated circuit according to the present invention, and FIG. 3 is a block diagram showing the structure of a conventional semiconductor integrated circuit. 1... Original clock generation circuit 2... Frequency dividing circuit 3...
・Other circuits 4... Frequency division value register 5... Frequency division value setting means 7... Selector 8... Reset signal input pin 61, 62, 63, 64... Initial frequency division value setting means 91, 92, 93...Initial frequency division value select pins In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The original clock supplied by the clock pulse generation circuit is divided by the division ratio set by the program and used as the basic clock for operation by the program, while when operating not by the program, a division ratio other than the program is set. In a semiconductor integrated circuit in which a source clock is divided by a frequency division ratio set by a frequency division ratio and used as a basic clock for operation, the frequency division ratio setting means can set a plurality of frequency division ratios, and the division ratio setting means can set a plurality of frequency division ratios. 1. A semiconductor integrated circuit comprising means for selecting an exponent frequency division ratio.