JPH02294126A - Data multiplexer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data multiplexing device that multiplexes a plurality of input data, and particularly to a clock supply means for multiplexing circuits in multiple stages. This invention relates to an improved data multiplexing device.

(Prior Art) Conventionally, data multiplexing devices for multiplexing input data have been widely used not only in communications but also in fields such as digital arithmetic processing. In data multiplexing, the larger the amount of information, the faster the transmission speed of the multiplexed data becomes. Therefore, when using multiple stages of multiplexing circuits, the multiplexing circuits in the later stage (higher order group) are used in the earlier stage. The timing of taking in the output data of the (low-order group) multiplexing circuit is important.

FIG. 6 is a block diagram showing a schematic configuration of a conventional data multiplexing device. n:1 after the m:n multiplexing circuit 61
It has a two-stage configuration in which multiplexing circuits 62 are connected,
The timing signal for taking in data is generated based on the clock signal of the subsequent stage. Here, since the load signal frequency when the input data is read by the multiplexing circuit 62 in the later stage (higher order group) is fax/n, this signal is generated in the multiplexer circuit 62 in the later stage to multiplex the lower order group. By feeding back to the circuit 61 and further providing a timing adjuster for the input data and the load signal, the timing at which the multiplexing circuit 62 of the higher order group takes in data is adjusted.

Note that the multiplexing circuits 61 and 62 are shift register type multiplexers (MUX). For example, 2:1 MU
Assuming X, the D flip-flop (
DFF) 7172, selector 73, 74 and frequency divider 75
Consists of etc. Data D1 is supplied to DFF71 via selector 73, the output of DFF71 is supplied to DFF72 via selector 74, and the output of DFF72 becomes the output of MUX. The clock signal is DFF71.7
2, the frequency is divided by 1/2 by a frequency divider 75, and the signal is supplied to selectors 73 and 74. Selector 73.
At 74, data to be selected is switched each time a clock is input. Therefore, the data rate of input data is 5 Gb
ps, the clock frequency fCK is 1 0 GH
z, the data D. , D2 is fcK/2-5GH
Loaded with a load frequency of z and multiplexed to lOGb
This becomes the output data of ps.

However, this type of device has the following problems. In other words, it is necessary to match the timing at which the output data from the low-order group multiplexing circuit is taken in by the high-order group multiplexing circuit. To do this, a load signal at the time of data input is created based on the clock frequency of the high-order group, and the input data is This can only be achieved by providing a timing adjuster. The higher the speed, the more important the timing regulator itself becomes, and the more difficult it becomes to design the circuit.

(Problem to be Solved by the Invention) Conventionally, when multiplexing circuits are configured in multiple stages and a load signal is generated to take in input data based on the clock frequency of a higher order group, output data from a lower order group and load Timing adjustment with the signal was required, and this timing adjustment was extremely difficult.

The present invention has been made in consideration of the above circumstances, and its purpose is to improve the timing of the output data from the low-order group and the load signal in the high-order group, 2! J adjustment is no longer necessary,
An object of the present invention is to provide a data multiplexing device that facilitates data transfer from a low-order group to a high-order group.

[Structure of the Invention] (Means for Solving the Problem) The most important point in a multiplexing circuit is the timing at which input data is taken in, and once that data is taken in, there is no need to multiplex the data. is not a problem. Conventionally,
Because the load signal for capturing input data was generated based on the clock signal of the higher-order group, there was a time lag between the output data of the lower-order group, that is, the input data to the higher-order group, and the load signal. Therefore, if a signal that is synchronized with the output data on the low-order group side is used as it is as a load signal on the high-order group side, no time lag will occur.

The present invention focuses on such points, and provides a data multiplexing device that multiplexes data using multiple stages of multiplexing circuits.
The multiplexing circuit at the subsequent stage is operated based on the clock of the multiplexing circuit at the previous stage.

The present invention also provides a data multiplexing device that multiplexes data using multiplexing circuits in multiple stages, in which a selector is used to select different input data at the rising and falling edges of a clock, and the input data rate and clock Using selector-type multiplexing circuits with matching frequencies, the frequency fCK of the clock input to the previous-stage multiplexing circuit is multiplied by m/n between adjacent multiplexing circuits. In this case, a frequency multiplier is inserted to supply the converter circuit.

(Function) According to the present invention, since the load signal at the time of data input on the high-order group side is generated based on the clock on the low-order group side, timing adjustment between the output data from the low-order group and the load signal is possible. This becomes unnecessary, and data transfer from the lower-order group to the higher-order group can be easily performed. At this time, the condition is that the input data rate and clock frequency match.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a block diagram showing the basic configuration of a multiplexing device according to a first embodiment of the present invention. Figure rl110 is a man multiplexing circuit on the low-order group side, and the output signal of this multiplexing circuit 10 is transmitted to the n:1 multiplexing circuit 20 on the high-order group side.
is supplied to. The clock (frequency fCK) is supplied to the multi-market circuit 10, and within this multiplex circuit 10, the clock whose frequency is multiplied by m/n is supplied to the multiplex circuit 20. In other words, the clock frequency f is m/n times higher than the clock frequency fcκ on the low-order group side. 8・m/
n operates the multiplexing circuit at the subsequent stage.

Figure 2 is a block diagram that shows Figure 1 in more detail. Here, an 8:1 multiplexer (hereinafter MUX
(abbreviated as ) will be explained as an example.

The 8:1 MUX itself is a tree-like configuration of 221 MUXes. That is, the input data is supplied to the first stage MUX 31, ~314, respectively, and these MUX
The output data of U X 3 1 + to 314 is the second stage M U X 3 1 5 . Supply for 3 l b, M U X 3 1! ．． The output data of 3 1 6 is supplied to the third stage MUX 3 1 7. Then, input data from M U X 3 1 7 to 8
= 1 multiplexed data is output.

A clock fck is input to the first stage MUX31I~314, and this clock fCK is input to the exclusive OR (XOR) gate 32 and the delay circuit (D
Multiplyed by 2 due to L>33+, clock 2 f C
K is the second stage MUX31s. 31, is input. Furthermore, this clock 2fcκ is doubled by the XOR gate 322 and DL332, and the clock 4fcK is input to the third stage MUX317. Here, M U X 3 1 + ~ 31 of the first and second stages
6 corresponds to the low-order group multiplexing circuit 10, and the third stage MU
Does X317 correspond to the high-order group multiplexing circuit 20? .

FIG. 3 is a block diagram showing a specific circuit configuration of a 2:1 MUX. This circuit basically consists of a master-slave type D flipflop (hereinafter abbreviated as MS-DFF) and a 41.3-stage D flipflop (hereinafter referred to as TS).
-DFF) 42, a selector 43, etc. One of the input data is MS-
One signal is supplied to the DFF 41, and the other is supplied to the TS-DFF 42. The output data of each DFF 41 and 42 is supplied to a selector 43 and selectively output.

Clock signal fCK is MS-DFF41, TS-DFF
42 and selector 43, respectively. Note that 44, 45 and 46, 47 in the figure indicate buffer amplifiers, respectively.

Here, as shown in FIG. 4, the data Da input to the MS-DFF 41 is delayed by about 1/2 clock,
Data Db input to the FF 42 is delayed by approximately one clock. Da'Db' is data obtained by delaying Da and Db, respectively. The selector 43 receives the clock f cKL:! )
Data Da'Db' captured at rising and falling edges
This is to switch between. Therefore, the data Da and Db are multiplexed and output from the selector 43.

In the configuration shown in FIG. 2, the first stage MUX 311~
When the input data rate of 314 is I Gbps, fcK
- Input the IGHz clock. At that time, the first-stage MUX 3 1 1 to 314 take in data without timing adjustment, and the multiplexed data is transferred to the second-stage MUX 3 1 s . 3 l b. Second stage MUX31s. 31,
Here, the clock frequency fCK is doubled and inputted by the XOR gate 32 and D L 3 3 r.

Therefore, for an input data rate of 2Gbps, 2G}
! z clock is input, and data is taken in without timing adjustment, similar to the first stage. The third stage is also realized in a similar manner.

Thus, according to this embodiment, the clock input to the MUX in the previous stage is doubled and supplied to the MUX in the latter stage, and the clock signal (clock) that is fed to the MUX in the latter stage is the same as that of the MUX in the previous stage. Since it is synchronized with the output data, there is no time lag. Therefore, data can be easily transferred from the lower-order group side to the higher-order group side without providing a timing adjuster or the like.

FIG. 5 is a block diagram showing a schematic configuration of a second embodiment of the present invention. This embodiment differs from the previously described embodiments in that a multiplexing device is realized by combining circuits with different sampling rates for the same frequency.

Here, the low-order group is a MUX of 8=2, and the high-order group is 2:
1 MUX, the MUX50 on the low-order group side is a circuit with the same sampling rate as the clock, and the MUX on the high-order group side is a circuit with the same sampling rate as the clock.
20 is a circuit having a sampling rate twice that of the clock. Specifically, the lower-order group side is a combination of the shift register type MUX shown in FIG. 7 above. , the MUX on the higher-order group side is the selector type MU shown in FIG.
It is X.

In this case, although the input data rate of the low-order group and the clock frequency fCK are different, it is possible to make the input data rate of the high-order group and fCK the same. Further, on the low-order group side, a timing adjuster is required to adjust the timing of the input data rate and the load signal in the same way as in the conventional case, but on the high-order group side, there is no need for such a timing adjuster.

With such a configuration, multiplexing can be performed by supplying the same clock to adjacent multiplexing circuits. Furthermore, although the input data rate on the low-order group side and fCK are different, it is possible to make the input data rate on the high-order group side and fCK the same. In data multiplexing, it is particularly difficult to match the timing on the higher order group side, so it is effective to make the input data rate on the higher order group side and fCκ the same as in this embodiment.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented in four different ways without departing from the spirit of the invention. For example, the multiplexing ratio (man) of the multiplexing circuits of the low-order group and the high-order group is not limited to the embodiment, and can be changed as appropriate according to the specifications. Furthermore, some of the connections between adjacent multiplexing circuits in the first embodiment may include connections between multiplexing circuits as in the second embodiment.

[Effects of the Invention] As detailed above, according to the present invention, since the load signal at the time of data input on the high-order group side is generated based on the clock frequency on the low-order group side, the output from the low-order group Timing adjustment between data and load signals is not required, and a multiplexing device that facilitates data transfer from a low-order group to a high-order group can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a multiplexing device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing FIG. 1 in more detail, and FIG. 2 in:
4 is a timing chart for explaining the operation of the MUX in FIG. 3, and FIG. 5 is a block diagram showing a schematic configuration of the second embodiment of the present invention. 6 is a block diagram showing an example of a conventional multiplexing device, and FIG. 7 is a block diagram showing a -11-1 configuration example of the multiplexing circuit of FIG. 6. 10.20... Multiplexing circuit (selector method) 311~
314...2:l MUX 315 to 316 at the first stage port
...MUX317 of 2:l in the second stage...MUX32+ of 2=l at the mouth of the third stage. 322...XOR gates 33, 332...Delay circuit 41...MS-DFF 42...TS-DFF 43...Selector 50...Multiplexing circuit (shift register system) Applicant's agent Patent Attorney Suzue Takehiko '11$'i Fig. 2 Ihen missing {1 Mr. Toy; 0 O, 0. 0

Claims (4)

[Claims] (1) In a data multiplexing device that multiplexes data using multiple stages of multiplexing circuits, data multiplexing is characterized in that a subsequent stage multiplexing circuit is operated based on a clock of a preceding stage multiplexing circuit. Device. (2) In a data multiplexing device that multiplexes data using multiple stages of multiplexing circuits, between adjacent multiplexing circuits,
A data multiplexing device characterized by inserting a frequency multiplier which multiplies the frequency f_C_K of a clock inputted to an m:n multiplexing circuit in the previous stage by m/n and supplies the multiplied clock frequency f_C_K to the multiplexing circuit in the subsequent stage. (3) The multiplexing circuit is of a selector type that uses a selector to select different input data at the rising and falling edges of a clock, and the input data rate and clock frequency match. 3. The data multiplexing device according to item 1 or 2. (4) In a data multiplexing device that multiplexes data using multiple stages of multiplexing circuits, the preceding stage of a set of adjacent multiplexing circuits uses a shift register to take in data at the rising or falling edge of a clock. Data multiplexing is a register method, and the latter stage is a selector method that uses a selector to select different data at the rising and falling edges of the clock, and is characterized in that clocks of the same frequency are input to each multiplexing circuit. conversion device.