JPH02297222A - Central processing unit - Google Patents

Abstract

PURPOSE:To attain the simultaneous and parallel processes of plural programs and to increase the processing speed by actuating two program counters and general-purpose register groups independently of each other. CONSTITUTION:In an optional machine cycle, the output of a 1st program counter 7 is supplied to a main memory device and simultaneously a program read control signal is supplied to the main memory device from a timing/control circuit 6. Thus the corresponding instruction is read out of the main memory device and a CPU performs an action to the instruction designated by the counter 7. In the next machine cycle, the output of a 2nd program counter 7A is supplied to the main memory device and the CPU performs an action to the instruction designated by the counter 7A. In addition, the 1st and 2nd general-purpose register groups 8 and 8A corresponding to counters 7 and 7A respectively are provided as the processing results in the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of a central processing unit that is a main component of a computer system.

[Conventional technology]

As shown in FIG. 2, a normal computer system includes a central processing unit 1 that mainly performs arithmetic functions and control functions for various devices as a computer system, and a main memory that stores programs and data for the computer system. 2, and an input/output interior W that controls data input/output to the outside of the computer system.
It consists of 3.

As shown in FIG. 3, this type of central processing unit l includes an arithmetic logic circuit 4 that executes actual arithmetic operations, logical operations, etc. as a central processing unit, and an instruction decoding circuit 5 that decodes and decodes programs for the central processing unit. , a timing/control circuit 6 that controls various timings and various circuits based on the decoding of instructions by the instruction decoding circuit 5, and a program counter 7 that manages sequential access and operation of programs stored in the main storage device. and a general-purpose register group 8 as a storage area for processing results within the central processing unit.

and an arithmetic logic circuit 4. The instruction decoding circuit 5゜general-purpose register group 8 is connected to the internal data bus DB of the central processing unit, and the internal data bus is connected to the external data bus ODB shown in FIG. 2 through a data bus buffer (not shown). .

Program counter 7 and general-purpose register group 8 are each connected to an internal address bus AB of the central processing unit, and the internal address bus is connected to external address bus OAB shown in FIG. 2 through an address bus buffer (not shown). Further, the timing/control circuit 6 performs the following based on the instruction decode signal SD output from the instruction decode circuit 5.
It generates various timing and control signals and is connected to an external control bus OCD shown in FIG. 2 through an internal control bus CD and a control bus buffer (not shown).

Next, the actual operation of the central processing unit configured as described above will be explained. The output of the program counter 7 is supplied to the main memory device 2 through address buses AB and OAB, and the program read control signal from the timing/control circuit 6 is supplied to the main memory device 2 through control buses CB and OCB. According to this address information and read control, the corresponding instruction is read from the main storage device 2 and input to the instruction decode circuit 5.

This command is decoded by the command decode circuit 5, the operation corresponding to the command is determined, and the information is inputted as the command decode signal S to the timing/control circuit 6. The timing/control circuit 6 receives an instruction decode signal S.

The actual operation of various circuits is controlled according to the following. For example, when it becomes necessary to read data from the main memory device 2, address information and a data read control signal for the data are supplied to the main memory device 2, and the required data is read from the main memory device 2. is read into the central processing unit 1. Furthermore, when arithmetic processing is required, data necessary for the arithmetic processing is set in the arithmetic logic circuit 4, and the required processing and processing timing are controlled.

In addition, in this way, the central processing unit 1 for one instruction
The period of operation is generally called a machine cycle.

As shown below, by sequentially executing machine cycle operations according to the program, the central processing unit 1
will execute the requested program operations stored in main memory 2.

[Problems to be Solved by the Invention] However, in the conventional central processing unit, only one program counter was provided to control the execution order of the programs, so the central processing unit could execute the program at any moment. Only one program was allowed. Therefore, when attempting to perform multiple programming using a conventional central processing unit, each program is made to monopolize the central processing unit, and the monopolized state is maintained for an appropriate number of cycles. i! It was necessary to realize multiple programming by switching between each program at an instant. For this reason, a special program dedicated to switching the exclusive state is required to execute the switching, which poses a major problem in that the switching takes a considerable amount of time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a central processing unit that can process a plurality of programs simultaneously in parallel, shorten the time required to switch between programs, and speed up processing.

[Means for Solving the Problems] A central processing unit of the present invention includes an arithmetic logic circuit, an instruction decoding circuit, a timing/control circuit, a first program counter, and a first general-purpose register group. Furthermore, one or more second program counters independent of the first program counter, a second general-purpose register group corresponding to the number of second program counters, and a first program counter and a second program counter. Means are provided for each output of the counter to be periodically and alternately supplied to the internal address bus.

[Effect]

In this configuration, by operating the first and second program counters and general-purpose register groups independently,
A single central processing unit can simultaneously process multiple programs in parallel, making effective use of the central processing unit and realizing high-speed multiple programming on the central processing unit.

C Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of a central processing unit according to the present invention, and the central processing unit l shown in FIG.
Main storage device 2. The internal configuration of a central processing unit 1 in a computer system configured with an input/output device 3 is shown.

In FIG. 1, here, as a central processing unit, there is an arithmetic logic circuit 4 that executes actual arithmetic operations, logical operations, etc., an instruction decoding circuit 5 that decodes a program for the central processing unit, and instruction decoding by the instruction decoding circuit 2. a timing/control circuit 6 that controls various timings and various circuits based on the timing/control circuit 6; a program counter (first program counter) 7 that manages sequential access/operation of programs stored in the main memory; a general-purpose register group (first general-purpose register group) 8 corresponding to the first program counter 7 as a storage area for processing results in the central processing unit; It consists of a second general-purpose register group 8A corresponding to the program counter 7A.

Arithmetic logic circuit 4. Instruction decoding circuit 5. The first and second general-purpose register groups 8.8A are each connected to an internal data bus DB of the central processing unit, and this internal data bus is
It is connected to the external data bus ODB in FIG. 2 through a data bus buffer (not shown). First and second program counters 7.7A, first and second general purpose registers 8.
8A are each connected to an internal address bus AB of the central processing unit, and this internal address bus is connected to an external address bus OA in FIG. 2 through an address bus buffer (not shown).
Connected to B. The timing/control circuit 6 also receives an instruction decode signal SD output from the instruction decode circuit 5.
Based on this, various timing and control signals are generated and connected to an external control bus OCB in FIG. 2 through an internal control bus CB and a control bus buffer (not shown).

Next, the operation of the central processing unit of this embodiment will be explained.

The operation when only the output of the first program counter 7 is constantly supplied to the internal address bus AB is the same as the operation in the conventional central processing unit shown in FIG. 3, and therefore the description thereof will be omitted here. In this case, the output of the second program counter 7A will not be supplied to the internal address bus AB.

Next, when the outputs of both the first program counter 7 and the second program counter 7A are respectively alternately supplied to the internal address bus AB, the respective outputs of the first and second program counters 7.7A It is assumed that the supply of the data to the internal address bus AB is switched at the machine cycle cycle (the operation cycle of the central processing unit for one instruction).

First, in any machine cycle, the output of the first program carantuff is supplied to the main memory 2 through the internal address bus AB, and the program read control signal from the timing/control circuit 6 is supplied to the main memory through the internal control bus CB. Supplied to device 2. According to these address information and read control, the main memory device 2
A corresponding instruction is read out from the instruction decoding circuit 5 and input to the instruction decoding circuit 5. The instruction is decoded by the instruction decode circuit 5, the operation corresponding to the instruction is determined, and the information is sent to the timing/control circuit 6 as an instruction decode signal SD.
is input to. The timing/control circuit 6 controls the actual operations of various circuits according to the instruction decode signal SD. Under the control of the timing/control circuit 6, the central processing unit executes operations in response to instructions specified by the first program counter 7.

In the next machine cycle, the output to the second program counter 7 is supplied to the main memory 2 through the internal address bus AB, and the timing/control circuit 6
A program read control signal is supplied to the main storage device 2 through the internal control bus CB.

According to these address information and read control, the corresponding instructions are read from the main memory device 2 and input to the instruction decoding circuit 5. The instruction is decoded by the instruction decode circuit 5, the operation corresponding to the instruction is determined, and the information is sent to the instruction decode signal S. The signal is input to the timing/control circuit 6 as a signal. The timing/control circuit 6 controls the actual operations of various circuits according to the instruction decode signal SD. According to the control of the timing/control circuit 6, the second
The central processing unit executes an operation corresponding to an instruction specified by the program counter 7A.

Here, the operations of the first and second program counters 7.7A are independent of each other, and the program areas designated by the respective program counters are independent of each other. Therefore, two programs are simultaneously processed in parallel on one central processing unit by alternately executing the operations in the machine cycle cycle described above for each program counter.

In the embodiment shown in FIG. 1, in addition to the first program counter 7, there is one second program counter 7A.
Although a case has been described in which one second general-purpose register group 8A corresponding thereto is provided, there may be a plurality of second program counters and a plurality of second general-purpose register groups.

[Effects of the Invention] As explained above, the present invention includes one or more second program counters and a second general-purpose register group that are independent of the first program counter, so that one central processing unit This allows multiple programs to be processed in parallel at the same time. This has the effect of making effective use of the central processing unit and realizing high-speed multiple programming on the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a central processing unit according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of a conventional computer system, and FIG. 3 is a schematic block diagram of a conventional central processing unit. 1...Central processing unit, 2...Main storage device, 3...
Input/output device, 4... Arithmetic logic circuit, 5... Instruction decoding circuit, 6... Timing control circuit, 7... First
program counter, 7A... second program counter, 8... first general purpose register group, 8A... second general purpose register group, AB... internal address bus, D
B...Internal data bus, CB...Internal control bus, SD...Instruction decode signal, OAB...External address bus, ODB...External data bus, OCB...
...External control bus.

Claims (1)

[Claims] 1. A first general-purpose register group that constitutes a computer system together with a main memory device that stores programs and data, and an input/output device that controls input and output of data, and that has an arithmetic logic circuit and a plurality of general-purpose registers. , a first program counter, an instruction decoding circuit, and a timing/control circuit, each circuit is connected by an internal data bus and an internal address bus, and the output of the program counter is transmitted through the internal address bus. In the central processing unit that sequentially reads programs stored in the main memory by supplying them to the main memory and executes processing, one or more second programs independent of the first program counter. counter and this second
a second general-purpose register group corresponding to the number of program counters; and means for periodically and alternately supplying each output of the first program counter and the second program counter to an internal address bus. A central processing unit characterized by: