JPH02302042A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To set an impurity concentration in a source region and a drain region to a desired high value without increasing an impurity concentration near a channel, to reduce a resistance of an impurity diffusion layer and to make a contact characteristic with a wiring part good by a method wherein, after a sidewall of a gate electrode has been formed, impurities are implanted into the source region and the drain region. CONSTITUTION:A gate electrode 3 is formed; after that, an oxide film 4 is formed; first impurity diffusion layers 5a, 5b are formed in a source region and a drain region. Then, an oxide film is deposited by a CVD method; after that, a gate sidewall 6 is formed by using an ordinary method. Then, second p-type impurity ions are implanted; second impurity diffusion layers 7a, 7b are formed in the source and drain regions. Then, an interlayer insulating film 8 of PSG or the like is deposited; contact holes 9a, 9b are made in the interlayer insulating film 8 on the source and drain regions; after that, TiW 10 and aluminum 11 are deposited; after that, a wiring pattern is formed; thereby, an ohmic contact can be realized easily by implanting second impurities.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that can form a highly concentrated impurity diffusion layer that suppresses the short channel effect of an MO3 type transistor. .

(Prior Art) With the miniaturization of MO3 type transistor elements, problems such as short channel effects that impede the miniaturization of the elements have arisen.

This short channel effect is enhanced by impurity diffusion from the source and drain regions to below the gate electrode. This will be explained with reference to the drawings.

As shown in FIG. 2(a), the gate electrode 2 has a gate length.
When the impurity diffusion layers 25a and 25b of the source/drain region are formed by the conventional method on the silicon substrate 21 having the impurity diffusion layer 25, the value of the channel length β is
It is determined by the distance between a and 25b. After forming the impurity diffusion layers 25a and 25b in the source and drain regions, during the high-temperature process that the wafer undergoes, impurity atoms constituting these impurity diffusion layers 25a and 25b are thermally diffused not only vertically but also laterally. Moving. thus,
As shown in FIG. 2 et al., the channel length l decreases in the direction of the arrow, increasing the short channel effect. To this end, attempts have been made to form shallow junctions by using elements with a small diffusion coefficient in the semiconductor substrate as impurities in the source/drain regions. In particular, there is a problem that there is no suitable element for the p-type impurity other than boron (B), which has a large diffusion coefficient, and shallow junctions cannot be formed using normal methods. The conventional method used to solve this problem was to reduce the amount of impurity doped into the source/drain regions, thereby suppressing the diffusion of impurities into the channel region.

(Problem to be Solved by the Invention) However, in the MOS transistor formed by the above method, since the impurity concentration of the impurity diffusion layer is kept low, the resistance of the impurity diffusion layer of the source/drain region is low. In addition, the contact resistance between the impurity diffusion layer and the wiring was also high. These parasitic resistances
This lowers the effective potential difference between the drains, and particularly deteriorates performance such as the gain of the transistor. Furthermore, when using a high melting point metal or its silicide as a wiring material or barrier metal, if the impurity concentration in the impurity diffusion layer is not high enough, contact resistance will significantly increase and/or non-ohmic behavior will occur, resulting in poor contact characteristics. It became a thing.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that forms an MO3 type transistor with low impurity diffusion layer resistance and low contact resistance without increasing the short channel effect. This is what we provide.

(Means for Solving the Problems) The present invention is a method for manufacturing a semiconductor device having an MO3 type transistor, which includes a first impurity implantation step of implanting impurities into a source region and a drain region after forming a gate electrode; The above object is achieved by including a step of forming a sidewall of an electrode, and then a second impurity implantation step of implanting impurities into the source and drain regions.

(Function) In the present invention, an impurity diffusion layer (first impurity diffusion layer) is formed in the source/drain region including directly below the region where the gate sidewall is formed by the first impurity implantation step into the source/drain region. It is formed.

A high concentration impurity diffusion layer (second impurity diffusion layer) is formed by the second impurity implantation step after forming the gate sidewall.
is formed on the first impurity diffusion layer. By forming this second impurity diffusion layer, the impurity concentration in the source/drain regions increases, and the resistance of the diffusion layer and the contact resistance with wiring formed in a later step are reduced. However, because the gate sidewall exists as a mask for ion implantation, the second impurity implantation does not increase the impurity concentration in the diffusion layer directly under the gate sidewall, and the impurity diffusion layer from the source/drain region to the channel region does not increase. entry is suppressed.

(Example) An example of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(a) are schematic cross-sectional views showing a method of manufacturing a p-channel MO3 type transistor of the present invention.

First, a gate insulating film 2 and a gate electrode material are formed on an n-type silicon substrate 1 by a normal method, and then the gate electrode is patterned using photolithography technology, and a gate electrode 3 is formed by etching. Figure 1(a)). Here, the gate length is, for example, L=1.5μ
Let it be m.

Next, by an oxidation process, the source/drain regions 5 and
An oxide film 4 is formed on the surface of the gate electrode 3. Increase the film thickness to 15
By setting the number of people as 0 to 400, during subsequent impurity ion implantation,
Impurity ions are prevented from being deeply implanted into the gate electrode 3 and source/drain regions 5. After the oxidation process, as a first p-type impurity ion implantation process, BP2 ions were accelerated at an energy of 60 keV and a dose of I x 10I5.
A first impurity diffusion layer 5a is formed in the source/drain region by implanting 10l5.

5b (Fig. 1 et al.)).

Next, after depositing an oxide film using the CVD method, gate side walls 6 are formed using a normal method (FIG. 1(C)).
). The thickness of the gate side wall 6 at this time is 200 mm.
It is preferable to set it as 0-4000A. If the thickness of the gate sidewall 6 is too small, the impurity implanted by the second p-type impurity ion implantation will easily diffuse into the channel region l. If the thickness is too large, the parasitic resistance of the source/drain regions increases.

Next, BF is used as the second p-type impurity ion implantation.

Accelerate ions with energy of 60 keV and dose of 2x10
rs cm 2 to form second impurity diffusion layers 7a and 7b in the source and drain regions (FIG. 1(d)).
).

Next, an interlayer insulating film 8 such as PSG is deposited, and a heat treatment that also serves as impurity activation is performed to interlayer insulating film 11j! 8 is reflowed (FIG. 1(e)). Thereafter, contact holes 9a and 9b are formed in the interlayer insulating film 8 over the source/drain regions using a conventional method (FIG. 1(f)), and then a wiring material is deposited by sputtering. Aluminum containing silicon is usually used as a wiring material. However, in order to prevent contact failure caused by mutual diffusion of both substances at the interface between aluminum and silicon substrate 1, a barrier metal is formed at the contact interface in this embodiment. As the barrier metal, TiW, TiN, etc. are often used. In this example, TiW was used.

After depositing TiWlo and aluminum 11 as wiring materials, a wiring pattern is formed by a normal method (first
Figure (hot water).

When using TiW as a barrier metal, an ohmic contact cannot be formed unless the surface impurity concentration of the P-type impurity diffusion layer is 8 x 10 "cl' or more. However, if the method of the present invention is used, the ohmitter can be formed by the second impurity implantation. Contact can be easily achieved.

Note that if the ratio of the doses in the first and second impurity implantation steps is in the range of 1=1 to 1:5, the resistance of the impurity diffusion layer and the contact resistance with the wiring can be reduced without deteriorating the transistor characteristics. can be sufficiently reduced.

(Effects of the Invention) According to the present invention, the impurity concentration in the source/drain region can be set to a desired high value by the second impurity implantation without increasing the impurity concentration near the channel of the MO3 transistor. Therefore, the resistance of the impurity diffusion layer can be reduced and the contact characteristics with the wiring can be improved.

Furthermore, the short channel effect is suppressed, which is effective for miniaturization.

[Brief explanation of drawings]

FIGS. 1A to 1C are diagrams for explaining each step of an embodiment of the present invention, and FIGS. 2A to 2D are diagrams for explaining a conventional example. L21...p-type silicon substrate, 2.22...gate insulating film, 3.23...gate electrode, 5a, 5b...
First impurity diffusion layer, Ta, Tb... Second impurity diffusion layer, 6... Gate side wall, 8.28...
...Interlayer insulating film, 10...TiW, 11...aluminum, 25a, 25b... impurity diffusion layer. that's all

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device having a MOS transistor, which comprises: a first impurity implantation step of implanting impurities into a source region and a drain region after forming a gate electrode; A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor device, and a second impurity implantation step of implanting impurities into the source region and the drain region.