JPH02303049A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Units of the Invention) (Industrial Application Field) The present invention relates to a semiconductor device in which a groove is formed in a semiconductor substrate and an element isolation insulating film is buried in the groove to isolate elements. It relates to its manufacturing method.

(Prior Art) In semiconductor integrated circuits in which miniaturized elements are integrated at high density, element isolation technology for electrically isolating each element is important. The element isolation method that has been commonly used so far is the so-called LOCO3 method, in which a thick oxide film is buried in the element isolation region by selective oxidation. But with this method,
In high-density integrated circuits with processing dimensions of 1 μm or less, it is difficult to obtain sufficient element isolation withstand voltage with a minute element isolation width.

In contrast, a method has been proposed in which an element isolation trench is formed in a substrate using dry etching, and an isolation insulating film is buried in this trench by a CVD method.

In that case, there are two methods: forming the element isolation trench with vertical sidewalls (Japanese Patent Application Laid-Open No. 57-170547), and a method of forming the trench with a constant inclination angle (Japanese Patent Application Laid-Open No. 58-210634).
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In the former method, although it is possible to obtain a device with a sufficiently high element isolation withstand voltage in small dimensions, deterioration of cutoff characteristics is observed when MOS transistors are integrally formed. The situation is shown in FIG. The one-dot chain line in the figure shows the characteristics when the element isolation groove that the channel width direction of the channel region of the MOS transistor touches has an inclination of about 45@. When formed, leakage current becomes large in the subthreshold region as shown by the solid line. This is because when the channel region of a MOS transistor is in contact with an element isolation trench perpendicular to the channel width direction, it is difficult to dope the vertical sidewalls with impurities as a stopper in the channel by ion implantation. This is the result of working as a channel.

On the other hand, in the latter method, since the element isolation groove is inclined, it is easy to dope impurities for stopping the channel, but the element isolation withstand voltage is slightly inferior to that in the case of having vertical sidewalls. FIG. 5 shows this situation. Curve A in FIG. 5 represents the case where the isolation trench has an inclined surface as shown in FIG. 6<a).
This is the punch-through withstand voltage between the n-type layers sandwiching this, and curve B is the punch-through withstand voltage in the case of having vertical sidewalls as shown in Figure 6(b).As is clear from the figure, the width of the element isolation trench When the width becomes smaller than 1 μm, the withstand voltage in the device isolation trench with the sloped surface becomes smaller than that in the vertical surface.In addition, when using the sloped sidewall, the device isolation width must be made smaller than when using the vertical sidewall. I can't.

(Problems to be Solved by the Invention) As described above, in the conventional device isolation technology in which a trench is formed and a device isolation insulating film is buried in the groove, a fine device isolation width is sufficient without causing deterioration of device characteristics. There was a problem in that it was not possible to obtain a high element isolation breakdown voltage.

An object of the present invention is to provide a semiconductor device having an element isolation structure that solves such problems, and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a semiconductor substrate in which a groove is formed in an element isolation region,
In a semiconductor device having a structure in which an isolation insulating film is embedded in this trench and a MOS transistor is formed in a region surrounded by the isolation insulating film, the sidewall of the isolation trench in the channel length direction of the MOS transistor is approximately It is characterized in that the sidewalls of the element isolation trench in the channel width direction, which are vertical and in contact with the channel region, are inclined.

Furthermore, the method of the present invention is characterized in that the element isolation trenches having different inclination angles depending on the direction are formed in a single etching process using directional dry etching with different etching conditions depending on the direction. .

(Function) According to the present invention, by providing an element isolation groove in which the sidewalls that affect the element characteristics have a certain slope, and the other sidewalls are substantially vertical, it is possible to increase the density of elements without impairing the element characteristics. Integration can be realized. That is, when integrating MOS transistors, the sidewalls of the isolation trenches in contact with the channel width direction of the channel region are sloped surfaces, and the sidewalls of the isolation trenches in the channel length direction are substantially vertical. As a result, M
The cut-off characteristics of the OS transistor become excellent, and element isolation regions that do not directly affect element characteristics can be formed with sufficient breakdown voltage and minute dimensions.

Furthermore, according to the method of the present invention, by setting the directional dry etching conditions, it is possible to obtain element isolation trenches with different slopes in a single etching process, without increasing the number of process steps. Excellent characteristics and high integration of devices can be achieved.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) and 1(b) show the structure of a memory cell array section of an embodiment in which the present invention is applied to a MOS type dynamic RAM (DRAM). (a) is a plan view, and (b) is its AA' and BB' cross-sectional views. In the back view of (a), the capacitor electrode is omitted, and the metal wiring is
[Both the top view and cross-sectional view are omitted. Element isolation groove 2 (2a) is formed on p-'C25i substrate 1.

2b) is formed, and an element isolation insulating film 3 is embedded therein by the CVD method. Gate electrodes 6 (6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 are formed in each 5iefi area in the form of a long and narrow island isolated from the elements, respectively, with a gate insulating film 5 interposed therebetween.

62, . . . ) are formed, and an n+ type scattering layer 7 that is self-aligned with this gate electrode 6 and becomes a source and a drain is formed. A CVD insulating film 8 is formed on the substrate on which the MOS transistor is formed, a contact hole is made in this, and a capacitor F part electrode 9 that contacts the source of the MOS transistor is formed for each memory cell. There is. A capacitor insulating film 10 is formed on the surface of the capacitor lower electrode 9, and a capacitor upper electrode 11 serving as a cell plate is formed thereon. Although not shown in the figure, the AI! Wiring is formed. This Al wiring as a bit line is arranged in a direction intersecting the word line. Reference numeral 12 in the plan view (a) is the bit line contact portion.

The element isolation trench 2 has a different inclination angle depending on the direction. That is, the groove 2a in the channel length direction of the MOS transistor appearing in the AA' cross section is formed with vertical sidewalls, and
The groove 2b, in which the channel region of the MOS transistor appearing in the -B' cross section is in contact with the channel width direction, is formed with an inclined sidewall.

FIGS. 2(a) to 2(g) are cross-sectional views corresponding to FIG. 1(b) showing the manufacturing process of such a RAM.

The manufacturing process will be specifically explained. First, as shown in (a), a silicon oxide film mask 21 patterned by photolithography is formed in the element formation region of the p-type Si substrate 1. As shown in FIG. In the example, an oxide film with a thickness of 300 nm was used. Next, element isolation grooves 2a and 2b are formed by photo-excited etching as shown in FIG. In this example, CF and Br were used as the etching gas, and a 193 nm ultraviolet light beam from an excimer laser was irradiated. At this time, when looking at the channel width direction of the MOS transistor, the light beam was irradiated only in the vertical direction as shown in Figure 3 (a), and the beam was irradiated in the channel length direction while swinging as shown in Figure 3 (b). . As a result, the grooves 2a in the channel length direction are formed with substantially vertical sidewalls, and the grooves 2b in the channel width direction are formed with inclined sidewalls. °
The etching depth is 1 μm on the vertical sidewalls. In this method, a deposit 22 is formed on the side wall of the groove due to a polymerization reaction. This deposit 22 is removed by combustion in oxygen plasma.

Next, as shown in FIG. 2C, boron ions are implanted to prevent inversion of the element isolation region. Reference numeral 24 in the figure is a boron-containing ion implantation layer. Then, as shown in (d),
About 500 nm of silicon oxide PA3 is deposited by CVD. Then, by reactive ion etching, oxidation II! I3 is etched over the entire surface, leaving it only in the element isolation trench 2, as shown in (c). A heat treatment is further applied to activate the implanted impurity and form a p-type layer 4 as a channel stopper.

After this, the actual element forming process begins. That is, Fig. 2 (r
), a gate insulating film 5 is formed by thermal oxidation,
A first layer polycrystalline silicon film is deposited on this, and this is patterned to form a gate electrode 6 which also serves as a word line. Then, using the gate electrode as a mask, ions of, for example, As are implanted to form a source.

An n1 type layer 7 that will become a drain is formed. Thereafter, a CVD method is used to form an interlayer insulating film, for example, silicon oxide II! 8 is deposited, a contact hole is formed in this, a second layer multicrystalline silicon film is deposited, and the capacitor lower electrode 9 of each memory cell is formed by patterning. After thermal oxidation is then performed to form a capacitor insulating film]0, a third layer polycrystalline silicon film is deposited and patterned to form a capacitor upper electrode 11. After this, although not shown, an interlayer insulating film is further deposited, and contact holes are opened to form Afi interconnects that will become bit lines.

According to this embodiment, the element isolation trench 2b in contact with the channel width direction of the MOS transistor constituting the memory cell has a sloped surface, and an inversion prevention layer (channel stopper layer) formed by ion implantation is formed with a sufficient concentration. be done. Therefore, the cutoff characteristics of the MOS transistor are excellent. Furthermore, the element isolation trench 2a in the channel length direction of the MOS transistor is formed with vertical sidewalls, and with a trench width of 1 μm or less, a higher isolation withstand voltage can be obtained than in the case of a sloped surface. Also, since it is a vertical side wall,
It is also easy to make the width of the separation region small. As described above, a highly integrated DRAM with excellent characteristics can be obtained.

Furthermore, the method of this embodiment has the advantage that the process is simple, since element isolation grooves having slopes that differ depending on the direction can be obtained in -3 etching steps.

Note that the present invention is not limited to the above embodiments. For example, in the embodiment, two types of side walls are provided, a vertical side wall and an inclined side wall, but it is not necessarily necessary that one side wall is vertical, but it is necessary to have different angles of inclination in the two directions to provide optimal element isolation characteristics for each side wall. be able to. In addition, although photoexcited etching was used in the embodiment as a method for forming the side walls of element isolation trenches with different inclination angles, other directional dry etching methods that can vary the etching conditions depending on the direction, such as ion beam or electron beam, may be used. It is also possible to use etching methods using other energy beams such as etching. Further, the present invention is not limited to DRAM, but can be applied to other integrated circuits.

[Effects of the Invention] As described above, according to the present invention, by selecting the shape of the element isolation groove depending on the direction, miniaturization and high integration can be realized while optimizing the element characteristics. Further, according to the method of the present invention, such optimization of device characteristics and high integration can be achieved by setting etching conditions without increasing the number of steps.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show D R of an embodiment according to the present invention.
2(a) to 2(g) are sectional views showing the manufacturing process, and FIGS. 3(a) and 3(b) illustrate the element isolation trench etching process. Figure 4 is a diagram showing how the characteristics of a MOS transistor change depending on the shape of the isolation trench, and Figure 5 shows how the characteristics of a MOS transistor change depending on the shape of the isolation trench. FIGS. 6(a) and 6(b) are diagrams showing the bunch-through breakdown voltage characteristics between the grooves, and are diagrams showing the measurement conditions for the punch-through breakdown voltage. DESCRIPTION OF SYMBOLS 1...p-type Si substrate, 2... element isolation trench, 2a.
... Vertical side wall groove, 2b... Inclined side wall groove, 3... CV
D silicon oxide film (cord isolation insulating film), 4...p type layer, 5... gate insulating film, 6... gate electrode (word line), 7... n'' type layer (source, drain), 8...
-CVD silicon oxide film, 9... Capacitor lower electrode, 10... Capacitor insulating film, 11... Capacitor upper electrode. Applicant's agent Patent attorney Takehiko Suzue-AB-111hadatT3 Q Q ″0

Claims (3)

[Claims] (1) In a semiconductor device in which an element isolation groove is formed in a semiconductor substrate, an insulating film for element isolation is embedded in the groove, and a MOS transistor is formed in a semiconductor region surrounded by the element isolation groove, the MOS transistor A semiconductor device characterized in that the sidewalls of the isolation groove in the channel length direction are substantially vertical, and the sidewalls of the isolation groove in the channel width direction that contact the channel region are inclined. (2) A step of forming an element isolation groove in the semiconductor substrate by directional dry etching, a step of embedding an insulating film for element isolation in the element isolation groove, and a step of forming an element in the semiconductor region surrounded by the element isolation groove. In the step of forming the element isolation trench by dry etching, etching conditions are set so that sidewalls with different inclination angles are obtained in a cross section in one direction and a cross section in a different direction. A method for manufacturing a featured semiconductor device. (3) The dry etching is an excitation etching method in which an excitation energy beam is irradiated at the same time as etching gas is supplied. By swinging the excitation energy beam in one direction, the side walls of the element isolation grooves in that direction are almost perpendicularly 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: