JPH02305472A - Gate array with built-in cpu and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a gate array to be easily designed and to be easily predicted in specification and performance of product before design by a method wherein a wiring pattern is provided to connect the intermediate point of a bus line with the signal terminal of a central processing unit core and the signal terminal of one of cell groups respectively. CONSTITUTION:A CPU core and two or more bus lines b1, b2,... bn arranged, at least, along one side of the CPU core are provided in a chip. A cell Cij is composed of basic cells BCij, and the wiring Wi of the cells Cij with the bus lines b1, b2,... bn is made between the signal terminals of the cells Cij with line-like bus lines b1, b2,.... By this setup, the prediction of wiring can be facilitated in a design phase, wirings can be made uniform in length, and the prediction of wiring length can be easily made. Occupied channels are made uniform in number, the prediction of the number concerned can be facilitated, and signals can be easily made uniform in propagation delay time owing to the uniformity of wirings in length.

Description

[Detailed Description of the Invention] [Summary] Regarding a gate array device with a built-in central processing unit (CPU) and a method for manufacturing the same, a gate array with a built-in CPU that is easy to design and whose product specifications and performance can be easily predicted before designing, and its manufacturing method. A method comprising: a group of basic cells disposed within a predetermined area; a central processing unit (CPU) core; and a plurality of bus lines fixedly disposed along at least a portion of the periphery of the CPU core. and a wiring pattern connecting the intermediate point of the bus line and a signal terminal of the central processing unit core, and the intermediate point of the bus line and any signal terminal of the cell group.

[Industrial Field of Application] The present invention relates to an ASIC device and a method for manufacturing the same, and more particularly to a gate array device with a built-in central processing unit (CPU) and a method for manufacturing the same.

"Conventional Technology" ASICs include custom ICs and semi-custom ICs. Furthermore, standard cell type and gate array type are known for this semi-custom IC. In standard cell type ASIC, effective use of wiring area,
Designers manually layout the chips by taking into consideration the equalization of signal propagation delay times (AC characteristics). In this case, the manpower required for development becomes large.

In gate arrays, the arrangement of cells and macrocells and the layout of wiring between them are automated using CAD.Normally, wiring is automatically designed under the condition that the wiring length is minimized. At the initial stage of design, a predicted wiring length is calculated by simulation, and if this satisfies the specifications, a chip layout is performed and the actual wiring length is calculated by simulation. If the actual wiring length differs significantly from the predicted wiring length, the design is repeated again to satisfy the specifications.

[Problems to be Solved by the Invention] According to the conventional gate array manufacturing technology described above, it is difficult to accurately predict the performance of the gate array product before the design is finalized.

An object of the present invention is to provide a gate array with a built-in CPU and a method for manufacturing the same, which is easy to design and whose performance can be easily predicted before designing.

Another object of the present invention is to provide a gate array with a built-in CPU and a method for manufacturing the same, in which signal propagation delay times can be easily made uniform.

[Means for Solving the Problems] According to the present invention, in a gate array with a built-in CPU, C
A plurality of bus lines are arranged in advance along at least one side of the PU core. Connection between each cell and these pre-arranged bus lines is made between a signal terminal of each cell and a plurality of pre-arranged bus lines.

FIGS. 1A and 1B are diagrams explaining the principle of the present invention.

Figure 1 (A) shows the master chip before slice design.In addition to the CPU'U core, there are multiple bus lines b1, b2 along at least one side of the CPU core.
・BN is set in advance. In other words, a large number of basic cells BCij are shown in the cell area S in the figure in which multiple bus lines have already been designed in a fixed pattern, but the wiring between them can be arbitrarily designed even in the fixed pattern. It can also be a pattern.

FIG. 1(B) shows an example of wiring performed on the master chip of FIG. 1(A), in which a cell is formed by a block of basic cells,
The wiring between each cell C1j and the bus lines bi, b2, etc. is connected to the signal terminal of each cell C1j and the linear bus line b1.
, b2 . . . In other words, since multiple bus lines b1 and b2 are provided in the fixed pattern along at least one side of the CPU core, wiring from each cell to these bus lines can be done to any point on the line. It can be made better and more uniform.

[Function] According to conventional automatic wiring, wiring is designed so that two or more points to be wired are connected, for example, by the shortest distance. As a result, the bus lines through which a group of signals passes are also distributed randomly, and their lengths tend to vary greatly. Therefore, it was also difficult to predict the wiring length.

According to the present invention, since wiring is performed between points and lines, the distance between them becomes uniform, and it becomes easy to predict the wiring length in advance.

Since the bus lines are fixedly wired together, the wire lengths for the bus lines can be made uniform, so that the signal propagation delay time can be made uniform.

Furthermore, since the wiring length becomes easier to predict, it is less likely that specifications will not be met and the design will be redesigned at the design stage.

Hereinafter, the present invention will be described in detail in comparison with the prior art with reference to FIG. 2 (A1-A3.81-B3). Second (AI
) to (A3) show slice designs according to the prior art, and FIGS. 2 (B1) to (B3) show wiring examples according to embodiments of the present invention. In the figure, the CPU (microprocessor) core is a large-scale macrocell. Therefore, the element arrangement and wiring pattern are specially designed and fixed. B, C, and D are Yacrocel. It is made by forming wiring between basic cells using a slicing process. It is assumed that wiring is made from the output terminal of the CPU to the input terminals 11, i2, and i3 of the macro cells B, C, and D.

FIGS. 2(A1) and (B1) show wiring examples when input terminals are provided on opposite sides of macro cells B and C1D.

In Fig. 2 (A1), from output terminal 1 to input terminal 1
This is the result of automatic design under the condition that the wiring lengths leading to 1, i2, and i3 are made the shortest.

Since the output terminal exists as one point, wiring is performed based on the concept of point-to-point connection.

In Figure 2 (B1), 1 of the bus line (bl)
Input terminals 11, 12, i3 of macrocells B, C, and D
An example of wiring is shown to connect the two over the shortest distance. There is no difference in terms of selecting the shortest wiring distance, but the difference is that the objects to be wired are input terminal points and bus line lines. Therefore, the wiring connecting the input terminal 11 of the macro cell B and the bus line is different from the wiring of the input terminals i2 and i3 of the macro cells C and D, unlike the case of FIG. 2 (A1).

FIG. 2 (A2) and (B2) show the case where the arrangement of macro cell B and macro cells C and D is exchanged.

Input terminal 11 of macro cell B and input terminals i2 and i3 of macro cells C and D are arranged on opposite sides. According to the prior art, when the output terminal 1 of the CPU and the input terminals 11 and i2.13 of macro cells B, C, and D are connected by the shortest distance, the result is as shown in FIG. 2 (A2).

On the other hand, instead of the CPU output terminal, the bus line (
bl) and the input terminals it and i2.13 of macro cells B, C, and D are connected by the shortest distance as shown in FIG. 2 (B2). In this case, branch wiring is provided at both ends of the main bus line that has been wired in advance.

Figure 2 (A3) and (B3) are
) In addition to the arrangement of the macro cells C and D, there is an obstacle between the CPU core and the macro cells C and D, making it impossible for the wiring to pass through.

FIG. 2 (A3) shows the input terminal 11 according to the prior art.
, i2, i3 are connected to the output terminals at the shortest distance. Since the CPU core and the macro cell C cannot pass due to an obstacle, the input terminals i2 of the macro cells C, D
, i3 is pulled upward in the figure and goes around macro cell D to C.
It is led to the output terminal of the PU core.

Figure 2 (B3) shows a bus line (b) along one side of the CPU.
This is the case when it is provided. Although an obstacle is provided, a bus line (bi l) is provided below it along one side of the CPU core, so the obstacle does not interfere with the wiring. Wiring can be done in the same way as in the case of .

The table below shows how long the wiring will be in the three cases explained above, comparing the conventional method and this method.
Figures in parentheses indicate the figure numbers in Figure 2.

According to the conventional method, the wiring length varies greatly from 11 to 32. On the other hand, in the case of this method, the wiring lengths are uniform at 26 in all three cases. Since it is easy to obtain a uniform wiring length, the wiring length can be easily predicted. Although short wiring lengths can be obtained using the conventional technology, since the worst case is often considered when predicting the wiring length, the conventional method often results in a prediction of 32. In the case of the conventional method, the difference in wiring length is as large as 21, which is preferable from the viewpoint of signal delay variation.In the case of the 0-wire method, there is a high possibility that problems will occur in signal processing. Since the length is uniform regardless of the arrangement, problems in signal processing are unlikely to occur.

Note that the unit of the wiring length is such that the length of the long side of the CPU core corresponds to 9, and the distance between macro cells B and D corresponds to 3.

In addition, in the case of the 6-wire method, which compared the number of channels occupied in these cases,
It is counted that 3 channels are occupied in each direction.

For example, in the case of FIG. 2 (A1), two X-direction wirings are provided in the wiring area between B and D, so
The number of occupied channels in the axial direction is 2, and Y
Since one wiring is provided in the Y-axis direction, the number of occupied channels in the Y-axis direction is one.

On the other hand, in the case of FIG. 2 (B1), in the upper wiring region, the number of wirings in the Y-axis direction increases by one, and the number of occupied channels in the X-direction increases by three due to the bus line. Therefore, the overall number of occupied channels increases by four to seven. Table 2 shows the number of occupied channels calculated for other examples in the same manner. Note that even if the wiring has the same Y value, if the wiring area is different, it is counted as a different channel.

Table 2 As shown in Table 2, according to the conventional method, the number of occupied channels is widely distributed from 3 to 10, whereas with this method, the number of occupied channels is distributed within a narrow range of 7 or 8. There is.

According to the wiring of the present invention as described above, the wiring length and the number of occupied channels are made more uniform compared to the prior art. Therefore, it is easy to predict the wiring length and the number of occupied channels before actually wiring.

Embodiment FIG. 3 is a plan view of a gate array chip according to an embodiment of the present invention. There is an I10 buffer r3a around the chip.
, 3b, and 3C13d, and a CPU core 4 as a large-scale macro cell and a basic cell region 5 are arranged in the internal region. Further, macro cells such as an interrupt controller, USART, counter/timer, etc. are mounted on the basic cell area 5 and exchange signals with the CPU core 4 via fixed wiring or the like. CPU core 4
A fixed wiring area 10 is provided in the peripheral area of the CPU, and a set of bus lines (bi l) are fixedly wired therein. These bus lines are connected to terminals inside the CPU core, and each bus line surrounds the CPU core in a loop. A plurality of basic cells BCij are arranged in the basic cell area 5.The basic cell BC1j is, for example,
A CMOS basic cell as described in the publication is used. The wiring between these basic cells BCij and the bus line (bi) is
This is the wiring between the j terminal and the bus line line. In addition to the bus line, it is also possible to place frequently used signal lines in the fixed wiring area 10)-6 Since the fixed wiring area 10 surrounds the CPU core 4, it is difficult to determine where on the CPU core 4 the signal terminals are located. It is also easy to connect the signal terminal to the loop-shaped wiring in the fixed wiring area 10.

FIG. 4 is a plan view of a gate array device according to another embodiment of the present invention. If the signal terminals of the CPU core can be effectively led out on one side, there is less need to provide a fixed wiring area surrounding the CPU core.

FIG. 4 shows an example in which a necessary amount of fixed wiring area 11 is provided along at least a part of the periphery of the CPU core 4 in such a case, that is, a fixed wiring area 11 is provided along one side of the CPU core 4. 11, on which a plurality of bus wirings and other necessary wirings are arranged in advance. The signal terminals of the CPU core are connected to these bus wirings and other signal lines, and each page/y cell BCij is connected to these wirings in a point-to-line relationship.

FIG. 5 shows an embodiment of the pond of the present invention. In the embodiment of FIG. 3, a fixed wiring area 10 was provided surrounding the CPU core 4, but in this embodiment, in addition to this, A fixed wiring region 12 is further provided surrounding the basic cell region 5.

Bus lines and other wiring arranged in the fixed wiring area 10 are connected to the wiring area 12 surrounding the basic cell area 5.
When trying to connect the signal terminals of the basic cells BCij in the basic cell area 5 surrounding the basic cell area 4 to these wirings, no matter which side of the basic cell area 5 the wiring is drawn out, Good, therefore, the wiring length can be made most uniform.

Note that, similarly to this embodiment, the fixed wiring area 11 shown in FIG. 4 and the fixed wiring area 12 surrounding the other side of the basic area 5 may be combined.

In this way, a fixed wiring area is provided along at least one side of the CPU core of the gate array chip, and wiring for frequently used bus lines such as address buses and data buses, as well as other wiring as necessary, can be fixedly routed. By providing the basic cell, it becomes easier to design the wiring from the basic cell uniformly. The fixed wiring area is not limited to the case described above, and may be provided in various other areas, but it is necessary to provide it along at least a portion of the CPU core.

Although the present invention has been described above with reference to the embodiments, it will be obvious to those skilled in the art that the present invention is not limited to these, and that, for example, various modifications, improvements, combinations, etc. can be made.

[Effects of the Invention] As described above, according to the present invention, it becomes easy to predict wiring at the design stage in a gate array device with a built-in CPU.

The wiring length is made uniform, making it easier to predict the wiring length.

The number of occupied channels is equalized, making it easier to predict.

By making the wiring lengths uniform, it is easy to keep the signal propagation delay time constant, and therefore it is easy to prevent operational errors due to differences in signal propagation delay times.

[Brief explanation of the drawing]

1(A) and 1(B) are diagrams explaining the principle of the present invention. FIG. 1(A) is a plan view schematically showing the chip state before individual design, and FIG. 1(B) is an illustration of the principle of the present invention. Plan views schematically showing the designed chip according to the requirements, FIGS. 2 (A1) to (A3),
(B1) to (B3) are schematic diagrams showing examples of the wiring of the present invention compared with the conventional technology, and FIGS. B3) is a schematic diagram showing the case according to the embodiment of the present invention, FIG. 3 is a schematic plan view of a semiconductor chip of a gate array device with a built-in CPU according to the embodiment of the present invention, and FIGS. 4 and 5 are respectively according to the present invention. FIG. 6 is a schematic plan view of a semiconductor and a chip of a gate array device with a built-in CPU according to another embodiment of the present invention. In the figure, S cell area C1j cell Bcij basic cell bij bus line 1 chips 3a to 3d I10 buffer 4 CPU core area 5 base cell area 7
Peripheral resource circuit 10, 11.12 Fixed wiring area Wiring side of the present invention compared with the prior art Fig. 2 Fig. 3 11 - Fixed wiring area Other embodiment of the present invention Fig. 4 10.12 - m = Fixed Wiring area Other embodiments of the present invention

Claims (3)

[Claims] (1) Basic cell group (B
Cij); a central processing unit (CPU) core; a plurality of bus lines (b1, b2...) fixedly arranged along at least a portion of the periphery of the CPU core; an intermediate point of the bus lines; A gate array device with a built-in CPU, comprising a signal terminal of a central processing unit core, a wiring pattern (wi) connecting an intermediate point of the bus line, and a signal terminal of any of the cell groups. (2) Claim 1, wherein the plurality of bus lines (b1, b2...) are provided in a loop shape surrounding the CPU core.
The gate array device with a built-in CPU described above. (3) A starting pattern for creating a gate array device with a built-in central processing unit (CPU), which includes a cell area (S) in which a basic cell group (BCij) is arranged, a fixedly arranged CPU core, A starting pattern (Fig. 1 (A
)) in a storage device; a step of retrieving the starting pattern from the storage device and inputting desired wiring information to automatically design wiring between the plurality of bus lines and each cell; A process of automatically designing other wiring, a process of superimposing the automatically designed wiring pattern on the starting pattern to create a product pattern (Fig. 2 (B)), and a process of creating a semiconductor gate array device using the obtained product pattern. 1. A method of manufacturing a gate array device with a built-in CPU.