JPH0232159U - - Google Patents
Info
- Publication number
- JPH0232159U JPH0232159U JP1988109467U JP10946788U JPH0232159U JP H0232159 U JPH0232159 U JP H0232159U JP 1988109467 U JP1988109467 U JP 1988109467U JP 10946788 U JP10946788 U JP 10946788U JP H0232159 U JPH0232159 U JP H0232159U
- Authority
- JP
- Japan
- Prior art keywords
- load tester
- synchronous
- data
- equipment
- termination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Maintenance And Management Of Digital Transmission (AREA)
Description
第１図はこの考案の一実施例による多負荷試験
器の構成を示すブロツク図、第２図はこの考案の
他の実施例を示すブロツク図、第３図は従来の負
荷試験器のブロツク図である。
図中、１は試験対象となる交換機、２は多負荷
試験器、３はカードフレーム、４は市販のパソコ
ンシステムを利用した中央制御装置、５は回線終
端装置（ＬＴＵ）、６は信号制御装置（ＳＣＵ）
、７は電源装置、８は市販のパソコン本体である
中央処理装置（ＣＰＵ）、９はキヤラクタデイス
プレイ（ＣＲＴ）、１０はキーボード、１１はフ
ロツピーデイスクドライブ（ＦＤＤ）、１２はプ
リンタ、１３はクロツク発生回路、１４はクロツ
ク使用／不使用切替えスイツチ（ＳＷ１）である
。なお、図中、同一符号は同一又は相当部分を示
す。
Fig. 1 is a block diagram showing the configuration of a multi-load tester according to one embodiment of this invention, Fig. 2 is a block diagram showing another embodiment of this invention, and Fig. 3 is a block diagram of a conventional load tester. It is. In the figure, 1 is the exchange to be tested, 2 is a multi-load tester, 3 is a card frame, 4 is a central control unit using a commercially available personal computer system, 5 is a line termination unit (LTU), and 6 is a signal control unit. (SCU)
, 7 is a power supply, 8 is a central processing unit (CPU) which is the main body of a commercially available personal computer, 9 is a character display (CRT), 10 is a keyboard, 11 is a floppy disk drive (FDD), 12 is a printer, and 13 is a The clock generating circuit 14 is a clock use/non-use changeover switch (SW 1 ). In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
終端装置間用多負荷試験器において、クロツク発
生回路と、同期データ網間国際回線の分散型着信
及び中継制御信号方式用プログラムとを備えたこ
とを特徴とする多負荷試験器。 A multi-load tester for use between data terminal equipment and data line termination equipment for synchronous operation, characterized by being equipped with a clock generation circuit and a program for distributed termination and relay control signal system for international lines between synchronous data networks. Multi-load tester.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988109467U JPH0232159U (en) | 1988-08-19 | 1988-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988109467U JPH0232159U (en) | 1988-08-19 | 1988-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0232159U true JPH0232159U (en) | 1990-02-28 |
Family
ID=31345734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988109467U Pending JPH0232159U (en) | 1988-08-19 | 1988-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0232159U (en) |
-
1988
- 1988-08-19 JP JP1988109467U patent/JPH0232159U/ja active Pending
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