JPH0247187B2 - - Google Patents

Description

[Detailed Description of the Invention] In recent years, as power systems have become larger in scale, the capacity of equipment and lines has also increased, and when a large power source or load is dropped due to an accident or incorrect operation, it has a large impact on the stable operation of the system. I'm getting used to it. In order to deal with this tendency and ensure system stability, emergency control of power and frequency is required to prevent major disturbances in the system.

The present invention provides a system control device that can perform power flow-frequency control that satisfies such requirements.

First, FIG. 1 shows an example of a conventional system control device that performs power flow/frequency control. In Figure 1, O
is the power station busbar, O1 and O2 are the power supplies connected to the busbar, O3 and O4 are the main power transmission lines, 11...1n are the feeders, and the main power transmission lines O3 and O4 are connected to the busbar O via the disconnectors 103 and 104. It is also connected to the feeder 11,...1n and the disconnector 111,
... connected to O via 11n, and the respective currents are connected to CT203, 204 and 211, ..., 21n
The voltage of the bus O is measured by the PT20.

Furthermore, 30 is a frequency detection relay, which detects a frequency that changes significantly when there is a sudden change in the power flow of the power system, and serves as a stopper for confirming the sudden change in power flow of the power system.
31 is a converter that is energized by the voltage and current of the sum-connected secondary circuits of PT203 and 204 to generate a voltage (DC) proportional to the power flow to detect the power flow of the main line, and 311 to 31n are the converters 2 of PT20. Next and
A converter 32 is connected to the secondary of the CTs 211, 212, . , relay 3
0 and converters 31, 311, . . . , 31n.
From 311...31n, signals proportional to the power flows of main lines O3, O4, feeders 11,...1n are inputted, respectively, and power flow control amounts P, _P1 , _P2 ...P _o necessary to stabilize the system are input. is calculated and the target of power flow control is determined.

At this time, the power flow control amount is: Pc=P-KΔfPo: For power control (1, 1) Pc=P-KΔfPo/1-KΔf: For load control (1, 2) However, K=K _CT +K _L : System characteristic constant Δf: Permissible frequency fluctuation width Po: System capacity (amount set after online calculation) Calculate the above equations (1, 1) and (1, 2) using the internal circuit (analog or digital) in the device.

Next, based on this Pc, a combination of control amounts P ₁ , P ₂ ... P _o that minimizes Pc - ΣPi (i = 1, 2, ... n) and satisfies Pc < ΣPi is created in the device circuit. (hybrid or digital),
The device outputs the number of the feeder corresponding to the combination of control amounts P ₁ ... P _o selected as described above, and outputs an output to control the corresponding feeder only when frequency fluctuation is detected by the frequency detection relay 30. It will be output outside.

The above is an overview of the configuration and operation of the conventional method.This method is characterized by treating the system characteristic constant K and allowable frequency fluctuation range Δf as constants when determining the necessary power flow control amount Pc. Although it is effective in simplifying the equipment configuration, the width of the allowable frequency fluctuation Δf of the specifier is important, and the system characteristic constant K changes from moment to moment with the system configuration.
Despite the fact that the system capacity Po is changed as a calculated setting amount online from time to time, it is handled somewhat roughly. In particular, when improving the accuracy of system power flow control, fixing the constant K as offline cannot reflect changes in the constant K when the system configuration changes, resulting in problems such as excess or deficiency in calculating the required control amount. It turns out.

Therefore, the present invention solves these problems, enables power flow control to be performed with higher accuracy, and enables this control to be performed immediately in response to changes in the system configuration, thereby contributing to improving system reliability. .

Below, to explain the present invention, the principle of the present invention will be described. Fig. 2 shows a system phenomenon for explaining the principle of the present invention, where a is voltage, b is power flow, and c is frequency, each failure occurs. This shows the changes before, during the occurrence of a fault, and after the fault has been removed. In a, the voltage decreases during the failure (t _p ~ t _c ).
Part b shows that the effective portion of the power flow decreases during a fault, and in particular, the power flow further decreases to zero after a fault occurs, and c shows how the frequency changes with this change in power flow. This shows that. That is, during the occurrence of a fault (t _p to t _c ), the main power flow decreases, so the frequency increases (f _p →f _c ) and reaches f _c . However, if, for example, the power supply were to be disconnected due to fault removal, the flow would start to fall from f _c . Also, when the load is dropped, different changes occur depending on the amount of drop. The change in frequency after a fault is removed is the same as that during a fault, so to summarize, generally speaking, in a power system, when the power flow changes by ΔP, the frequency changes by Δf, and the relationship between the two is as follows. .

Δf/ΔP=-1/K・1/1+TS+μ(s)・1/P _p ...(1.3) where K: System characteristic constant P _p : System capacity T: System time constant μ: Function representing governor action To look at this relationship, for example, assuming that the governor does not work at T = 0.5 seconds or less, Δf/ΔP = -1/K (1-ε ^-t/T ) 1/Po... (1.4
), or more approximately, Δf/ΔP=-1/K・t/T・1/Po (1.5).

In short, for example, from 0.1 to failure occurrence and removal.
In a time period of about 0.2 seconds, Δf and ΔP are in a proportional relationship, and can be said to be proportional to K, T, and the time t after the failure occurs, as shown in equation (1.4).

In the present invention, using the above relationship, 1/K∆P/Po・1/T in the following formula ∆f=1/K∆P/Po・t/T is obtained from the relationship of ∆f−t during failure occurrence, By further correcting with ΔP caused by the fault, 1/KTPo can be obtained, and we focused on the fact that using 1/KTPo makes it possible to predict the frequency drop slope when the fault is removed to some extent. . That is, the rate of frequency change is inversely proportional to the system characteristic constant K, but the constant K is K = K _G + C _L , and since the following relationship exists, it depends on the system configuration (generator configuration).

K _G = K′・_o 〓 ⁱ⁼¹ Δf−ε _i /η _i・C _i K′: Constant, Δf: Frequency change width ε _i : Total dead band width (varies depending on the governor. For example, about 0.012 to 0.1%) η _i : Speed regulation rate C _i : Governor operating generator capacity ratio to system capacity As described above, K (system characteristic constant) changes greatly with the system configuration. That is, the time constant T can be calculated separately during online operation, and the time constant T is determined by the inertia constant M and the load characteristic D of the system, which is determined by the generator connected to the system. However, since it is highly unlikely that many generators connected to the grid will be disconnected at once, the time constant T can be considered to be approximately constant.

Taking all of the above facts into account, we can know that KT is known from the frequency change immediately after the occurrence of a system fault, and the time constant T of KT can be estimated in advance, so the system characteristic constant K can be calculated backwards.

Based on the above principle, the present invention separately calculates the system capacity and system time constant in a quasi-online manner, and uses this to estimate the system characteristic constant K more accurately than ever before, and similarly calculates the system capacity and system time constant in a quasi-online manner. The aim is to improve the accuracy (responsiveness) of system stabilization control. In other words, if the above K is used, the following equation expressing the required amount of stabilization control, Pc = P - KΔfPo (power supply control), Pc = P - KΔfPo / 1 - KΔf (load control), becomes even more difficult because K is estimated online. Accuracy can be improved.

Next, the general structure and operation of an embodiment of the present invention based on the above-mentioned principle will be described below.
In FIG. 3, numeral 33 replaces the conventional frequency detection relay and is an arithmetic unit having the function of detecting changes in frequency and power flow Δf, ΔP and estimating the system constant K(t) from this, and numeral 34 according to the present invention. In the control device, a value K(to) close to the value at the time of occurrence of system fluctuation is used as the value of Δf/ΔP(t)=K(t) calculated from the calculation judgment output of the arithmetic unit 33, and Pc( to) = P-K(to)・Δf・Po(to) ...For power control Pc(to)=P-K(to)・ΔfPo(to)/1-K(to)
)・Δf...The first function that calculates the case of load control and also uses this Pc (to) ΣPj − Pc = ε The value of ΣPj that minimizes the above formula and configures this
It has a second function of determining the set of Pj.

As mentioned above, in the case of the present invention, the arithmetic unit 33 and the control device 34 are very different from the conventional system, but in particular, the arithmetic unit 33 uses the constant K
The value of is estimated online, and has the configuration shown in FIG. The contents will be explained below.

In Figure 4, O is the bus bar, 1 is the beam and disconnector, 2
is a CT, 3 is a transformer, 4 is a line for measuring the power flow, and the computing unit 33 has the following configuration. First, 10 is a current/voltage (DC) converter, 1
1 is a voltage/voltage converter; 12 is a waveform shaping circuit that rectifies the waveform of the grid voltage to obtain a waveform close to a rectangular wave;
Reference numerals 13 and 14 designate sample-and-hold amplifiers that hold the value after converting the current into voltage, and the holding and resetting are performed in synchronization with changes in the voltage waveform, which will be described later. Further, 15 is a buffer amplifier that receives a DC voltage proportional to the system voltage from the converter 11, 16 is a sample-and-hold amplifier that also temporarily stores the DC voltage, and 17 inputs each of the above-mentioned power currents P and voltages V and converts them into digital data. The A/D converter 18 is a comparator that compares the instantaneous voltage value (output 15) and the held value (output 16), and responds to sudden changes in voltage, and detects system failures and opening/closing. I will do it.

Next, 20 is a zero point cross detector which generates a pulse when the rectangular voltage waveform-shaped by the waveform shaping circuit 12 crosses the zero point, and this output is given as a control pulse to a counter 21, which will be described later. Further, 22 is an oscillator that generates a reference pulse for discriminating the frequency from the system voltage waveform, and its output is given to the next gate 23. And the above counter 2
1 counts zero-point pulses generated when the voltage waveform passes a zero point, and supplies a signal to gates 23 and 24 via a processor 27 at every predetermined cycle of the system frequency. The gates 23 and 24 allow the pulses emitted from the counter 22 to pass through for a predetermined cycle.
1 is completed, it is closed to allow a predetermined pulse between cycles of the grid voltage to pass. 25 and 26 are registers that accumulate pulses that pass while the gate is closed. 23, 24, 25, and 26 are all controlled by a processor 27, which will be described later, to count and store pulses. 27 is a data processor, which includes a register 25 corresponding to the output data of the A/D comparator 17, the determination result of the comparator 18, the output of the voltage 0 point detector, the output of the frequency counter 21, and the number of clock pulses passing during a predetermined period; 26 output as input, sample hold amplifier (buffer amplifier) 13 to 16, A/D
Converter 17, gates 23, 24, register 2
5 and 26, and performs control and arithmetic judgment for providing a comprehensive judgment output to the output port 28.

To explain the operation of the configuration shown in FIG. 4, first, the input to the processor 27 will be described.
The voltage and current of the system are applied from PT3 and CT4 to the power flow converter 10, respectively, and their effective power is obtained as a DC voltage. This output is applied to the next-stage sample-and-hold amplifiers 13 and 14, but is controlled by a timing signal from the processor 27, and is sampled and held at the zero point of the rising edge of the A-phase voltage of the system voltage (for example), and is then sampled and held at the zero point of the rising edge of the A-phase voltage of the system voltage, and the rising edge after 1 c/s. It is designed to be reset at 0 points. With such control, the output of the sample-and-hold amplifier 13 is held for one cycle, and the output of the amplifier 14 is held for another cycle. Two values of the power flow are held by this circuit and sent to the processor 27 via the A/D converter 17 for integration or change detection.
is input to.

Next, the system voltage V is applied from the PT 3 to the converter 11 to become a DC voltage Vd, and then applied to the buffer amplifier 15 and the sample-and-hold amplifier 16, respectively. Similar to the above-mentioned flow, the sample-and-hold amplifier 16 is reset at the rising point of each cycle, and is held for one cycle. or,
This voltage is compared with the voltage at the rising point of the next cycle, and if there is a change in the system, the comparator 18
works. As a result, the interrupt input is sent to processor 2.
Give to 7. Furthermore, at the time of voltage 0, which passes every half cycle of the system voltage, the waveform shaping circuit 20 generates a pulse, which is counted by the counter 21. Based on this result, the gates 23 and 24 are alternately opened and closed, and the oscillator 22 generates a pulse continuously. The clock pulses to be used are stored alternately in registers 25 and 26. The contents of this register are read into the processor 27 in synchronization with the outputs of the waveform shaping circuit 20 and the counter 21, and are stored every predetermined cycle.

That is, the processor 27 calculates a value that is proportional to the period T of each cycle of the voltage waveform and inversely proportional to the reciprocal of the frequency, with the zero-point passing point of the grid voltage waveform as the time reference point.
It will be stored internally.

The above input will be explained in detail with reference to FIG. 5, which shows a schematic time chart. First, starting from the reference time _tO , the various quantities to be introduced into the processor 27 as the power flow, frequency, and voltage in the 1st, 2nd, etc. cycles are defined as the power flow P: P(1), P(2), P(3)... ...P(n) Frequency f: f(1), f(2), f(3)...f(n) Voltage V: V(1), V(2), V(3)...V(n ), and the various quantities of the circuit parts are expressed as: Output of power flow exchanger 10: Pd(t) Output of voltage converter 11: Vd(t) Output of counter 21: C(t) Output of gate 23: G _A (t) Output of gate 24: G _B (t) Output of register 25: R _A (t) Output of register 26: R _B (t) From the above explanation, the averaging of the power flow is P( 1)={Pd(to)+Pd(to+t ₁₁ )}1/2 P(2)={(Pd(to+T ₁ )+Pd(to+T ₁ +T ₂₁ }1/2 P(3)={(Pd(to+T _{2 )} ) + Pd (to + T ₂ + T ₃₁ )} 1/2 However, here, t ₁₁ is the time from the 0 point of the first half wave in Fig. 5, and t ₂₁ is the time from the 0 point of the first half wave to the 0 point of the second half wave. Time to point t ₃₁ is the time from the 0 point of the second half wave to the 0 point of the third half wave T ₁ is the period of the first wave in Fig. 5 T ₂ is the period of the second wave in Fig. 5 T ₃ is the period of the third wave in FIG. 5, and the same applies to the voltage V.

Regarding the frequency, if the output of the waveform shaping circuit 20 is VZ, then VZ=1
(t=to, to+t ₁₁ , to+T ₁ , to+T ₁ +t ₂₁ ,...) C=1 (t=to, to+T ₁ , to+T ₁ +T ₂ ) G _A (t)=1 to≦t≦to+T ₁ to+T ₁ +T ₂ ≦t≦to＋T ₂ ＋T ₃ ＋T ₁ G _B (t)=1 to＋T ₁ ≦t≦to＋T ₁ ＋T ₂ to＋T ₁ ＋T ₂ ＋T ₃ ≦t≦to＋T ₁ ＋T ₂ ＋T ₃
+T ₄ , therefore, R _A (1)=Pc(1) t=to+T ₁ R _A (2)=0 to+T ₁ ≦t≦to+T ₁ +T ₂ R _A (3)=Pc(3) t=to+T ₁ R _A (4)=0 However, Pc(1) is the total number of pulses passing through G _A from t=to to to+T ₁ , and Pc(3) is from t=to+T ₁ +T ₂ to t=to+T ₁ +T ₂ +
The total number of pulses passing at T ₃ , similarly, R _B (1)=0 to≦t≦to+T ₁ R _B (2)=Pc(2) t=to+T ₁ +T ₂ R _B (3)=0 to+T ₁ +T ₂ ≦t≦to＋T ₁ +T ₂ +
T ₃ R _B (4)=Pc(4) t=to+T ₁ +T ₂ +T _3However , Pc(2) is from t=to+T ₁ to T ₀ +T ₁ +T ₂
The total number of pulses passing through G _B , Pc(4), is t = to + T ₁ + T ₂ to to + T ₁ + T ₂ + T ₃
This is the total number of pulses passing through G _B during the period, and the frequency obtained by measuring the voltage waveform is f(1)=K/R _A (1)=K/Pc(1) f(2)=K /R _B (2)=K/Pc(2) f(3)=K/R _A (3)=K/Pc(3) f(4)=K/R _B (4)=K/Pc(4 ).

That is, the frequency is measured by counting the elapsed cycle every half cycle as a reference at the zero-point passing point of the voltage waveform, and expressing the period length of this cycle by the number of reference pulse counts.

The above analog quantities P(1), P(2), ...P(n), V
(1), V(2)...The sample hold signal and reset signal necessary to capture V(n) are the voltage waveform O.
When the signal passes through the point, it is generated by the waveform shaping circuit 20 and applied to the sample and hold amplifier, buffer amplifiers 13 to 16, and A/D converter 18 via the processor 27, so that synchronization can be maintained. Also, f(1),
The signals for data opening/closing and register reset necessary to take in the digital amount of f(2)...f(n) are generated by the counter 21 that counts the zero point pulses generated by the waveform shaping circuit 20, and are generated by the gate 23,
24 and registers 25 and 26, synchronization is maintained as in the case of reading the analog quantity described above.

Next, when arithmetic processing is performed based on P, V, and f taken in by the above configuration, the relationship between Δf and ΔP is Δf=K・Δt/T・ε ^-t/T as mentioned earlier. The first variation (Δf) ₁ is obtained by taking the average of the first three cycles and using this and the average before the accident, as follows: (Δf) ₁ = f(1) + f(2) + f(3)/3 -f(0), and similarly create the second variation (Δf) ₂ from the average of three consecutive cycles.

(Δf) ₂ = f(4)+f(5)+f(0)/3- f(1)+f(2)+f(3)/3 Next, similarly for the power flow, ΔP=P(1)+P( 2) +P(3)/3-P(0), and for the time interval, t=T ₁ +T ₂ +T ₃ +T ₄ +T ₅ +T ₆ /6 or T ₁ +T ₂ +T ₃ /3. Substituting again into equation (1.5), f(1)+f(2)+f(3)/3-f(0)/f(1)+f(2)
)+f(3)/3-P(0) =-1/K・1/T(T ₁ +T ₂ +T ₃ /3) 1/Po Find 1/KT from the above formula.

Then, after the next three cycles after the sudden voltage change, f(4)+f(5)+f(6)/3-f(1)+f(2)+f(3)/
3/f(4)+f(5)+f(6)/3-f(1)+f(2)+f(3)/
3 = 1/K.1/T (T ₄ +T ₅ +T ₆ /3) 1/Po The values are almost the same as in the above equation.

From the above, the value of KT is determined, and by knowing the system time constant T, the value of the system characteristic constant K is determined. In this way, the system characteristic constant K can be estimated from short-term measurements of ΔP and Δf triggered by a sudden voltage change.

Such estimation is generally possible based on the changes in ΔP and Δf when a system accident occurs, and if the system accident continues, for example, by about 0.1 SEC, the above f(1) ~
It is possible to sample up to f(6). If the dropout current is large after this and the system frequency continues to decrease, compare the system characteristic constant K obtained using the above changes with the system characteristic constant K obtained by measuring after the failure. If there is no difference, K is considered to be correct, and power flow control calculations can be performed using this system characteristic constant K.

Although this value may be different from the value set in the equipment before the accident occurred, the fact that it remains the same during and after the accident has occurred indicates a value closer to the current state of the system. This means that using this system characteristic constant K allows more realistic and highly adaptive control.

In addition, the value of the system time constant T is necessary because it is given as a divisor to KT when determining the system characteristic constant K, but this is due to the connection when determining Po (system capacity),
The difference from the actual value due to exclusion is determined to be within a certain range, so there is no problem in practice if this range is taken into account when calculating the system characteristic constant K from KT.

To summarize the effects of the invention as described above, (1) reliability is high because system characteristic constants estimated from the actual operating conditions of the system are used;

(2) Immediate response is high because it can be estimated even during a system accident.

(3) By distributing this function to various locations and centralizing the data, the accuracy of grid power supply operation will improve. It is expected that the performance will be further improved than before.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a conventional system control device, FIGS. 2 a to c are system phenomenon waveform diagrams for explaining the principle of the present invention, and FIG. 4 is a partial detailed configuration diagram of FIG. 3, and FIG. 5 is a diagram of output waveforms of each part of FIG. 4. O... Bus bar, O3, O4... Main power transmission line, 30... Frequency detection relay, 31... Converter, 32... Control device, 33... Arithmetic unit, 34... Control device, 10, 11
...Converter, 12...Waveform shaping circuit, 13, 14, 1
6... Sample hold amplifier, 15... Buffer amplifier, 17... A/D converter, 18... Comparator, 20... Cross detector, 21... Counter, 22
...Oscillator, 23, 24...Gate, 25, 26
...Register, 27...Processor, 28...Output port. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. It is installed at a predetermined main point in the system, and calculates the necessary planned power flow restriction amount in the event of a sudden change in power flow due to an accident or incorrect operation of the important power transmission line, based on the constant power flow of the important power transmission line at that point and the constant power flow of the target power transmission line. In a system control device that performs calculations to stabilize the system,
A system control device characterized by having a function of recalculating the planned power flow restriction amount by estimating a system characteristic constant from the amount of falling power that occurs at the time of an accident and the frequency fluctuation at the time of the accident.