JPH0247507Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is designed to
The present invention relates to an electrolytic capacitor leakage current determination device that simultaneously processes leakage current determination and disconnection determination in a large quantity and in a short time.

Conventionally, when determining whether the leakage current of an electrolytic capacitor is good or not and whether there is a disconnection, the leakage current is considered good if the current value flowing through the capacitor when a specified voltage is applied for a specified time is less than the leakage current specification. Detection of disconnection is determined by whether current flows or not, or by the presence or absence of capacitance, so separate measuring instruments are required to measure both characteristics, and simultaneous processing is not possible, so a large number of capacitors are required. The processing required a large amount of man-hours. As an example of the configuration of a leakage current measuring device, a commercially available micro-ammeter is used to apply a specified voltage for a specified period of time, and then the input terminals of the micro-ammeter are sequentially switched using a relay or the like to measure multiple electrolytic capacitors. A device that performs pass/fail judgment processing is adopted, and an example of a device for detecting the presence or absence of a disconnection is a bridge circuit that detects the presence or absence of a capacitance value, and a sequential switching circuit using a relay etc. to detect the presence or absence of a disconnection in multiple electrolytic capacitors. A device that performs judgment processing was employed. Therefore, there is a disadvantage that the device has a plurality of configurations and is relatively expensive.

An object of the present invention is to provide an apparatus for determining leakage current and disconnection of an electrolytic capacitor, which is capable of simultaneously determining leakage current and detecting disconnection, by improving the sub-points of the above-mentioned devices.

According to the present invention, the following circuits A, B, and C are provided, the reference input terminals of the circuit B are connected in parallel, and the input terminal of the reset signal SIG1 and the input terminal of the hold signal SIG3 of the circuit C are provided. , a device for determining leakage current quality and disconnection of an electrolytic capacitor is obtained, which is constructed by connecting the input terminals of the set signal SIG2 in parallel.

(a) Connect the anode side of the electrolytic capacitor to the positive potential side of the measurement power supply via a relay contact, and connect the cathode side to the input terminal of the current-voltage converter via a resistor, and further connect the negative potential side of the measurement power supply to the A current-to-voltage converter circuit with the potential side connected to the ground terminal.

(b) A comparison/judgment circuit in which the signal input terminal of the comparison/judgment device is connected to the output terminal of the current-voltage converter, and the reference input terminal is connected to the output terminal of the measurement reference value circuit.

(c) Connect the output terminal of the comparator to the S terminal of the first R-S flip-flop circuit, connect the output terminal of the 2-input OR circuit to the R terminal, and connect the output terminal of the 2-input OR circuit to the R terminal. A first R-S flip-flop circuit has a reset signal SIG1 and a hold signal SIG3 connected to each input terminal, an inverter circuit is connected to the Q terminal, and the cathode side of a light emitting diode is connected via a resistor. Connecting the output terminal of the comparison/judgment device to the R terminal of the R-S flip-flop circuit No. 2;
And the output terminal of the 2-input OR circuit is connected to the S terminal, the reset signal SIG1 and the set signal SIG2 are connected to each input terminal of the 2-input OR circuit, and an inverter circuit is connected to the Q terminal, and a resistor is connected. a second R-S flip-flop circuit to which the cathode side of the light emitting diode is connected through the second R-S flip-flop circuit;

Hereinafter, embodiments of the present invention will be described in detail based on FIGS. 1 to 5.

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a timer and signal diagram for operating the circuit of FIG. 1.

In Fig. 1, the positive potential side of the DC measurement power source E1,1 is the relay contact (rl ₁ -1 to n) 4 of the relay RL1, 3 driven by the charging time signal TIM1, 2.
are respectively connected to the anode terminals of the electrolytic capacitors under test (CX1 to n) 5 through the relay contacts (rl ₁ -1 to n) 4 on the unconnected side of the electrolytic capacitors under test (CX1 to n) 5. The terminals are connected in parallel and connected to the positive potential side of the DC measurement power source E1,1. The input terminal of the current-voltage converter (CONV1~n) 6 is the electrolytic capacitor under test (CX1~n) 5.
are connected to the cathode side of each via a resistor (R1 to Rn) 7, and the ground terminal side is connected in parallel and further connected to the negative potential side of the DC measurement power source E1,1.

Next, the signal input terminal of the comparator circuit (COMPA1 to n) 8 is the current voltage converter (CONV1 to n)
6 output terminals, and the reference input terminals are each connected in parallel, and the measurement reference value circuit REF
Connected to 9.

The first R-S flip-flop circuit (FFa
-1 to n) 10aS terminals are respectively connected to the output terminals of the comparator circuits (COMPA1 to n) 8, and the R terminals are connected to the two-input OR circuits (ORa-1 to
n) Connected to the output terminal of 11a, one input terminal of 2-input OR circuit (ORa-1 to n) 11a is connected in parallel and reset signals SIG1, 12
connected to. In addition, the remaining input terminal is connected in parallel, and FFa hold signals SIG3, 13
The Q terminal is connected to each inverter circuit (INV.a-1~n) 14a, and is connected to the cathode of the light emitting diode (LEDa-1~n) 16a via a resistor (Ra-1~n) 15. Relay RL ₂ 18 is connected and the anodes are connected in parallel and activated by LEDa.b power-on signal TIM17.
It is connected to the positive potential side of the light-emitting diode drive power source E ₂ 20 via the relay contact rl ₂ 19 of.

The R-S flip-flop circuit (FF
The R terminals of b-1 to n) 10b are connected to the output terminals of the comparator circuits (COMPA1 to n) 8, and the S terminals are connected to the two-input OR circuits (ORb-1 to
n) One input terminal of the two-input OR circuit (ORb-1 to n) 11b is connected in parallel and connected to the reset signal SIG12, and the remaining input terminal is In addition to being connected in parallel, it is connected to the FFb set signals SIG2 and 21, and the Q terminal is connected to each inverter circuit (INVb-
1~n) Connect 14b and then resistor (Rb-1~
n) Light emitting diode (LEDb-1
~n) Relay connected to the cathode of 16b and driven by Da,b power-on signals TIM2, 17
The RL ₂ 18 is connected to the positive potential side of the light emitting diode drive power source E ₂ 20 via the relay contact RL ₂ 19 .

Next, the operation of the circuit of the present invention will be explained using FIGS. 1 to 5. In general, the direct current flowing through a capacitor has a characteristic that it rises steeply at the start of charging and gradually decreases over time, and is expressed by the following equation (1).

i(t)=V/Rs・ε−t/CRs+i _a (t)+Ie…(1) where V: Applied voltage (V) Rs: Series insertion resistance (Ω) C: Capacitance i _a (t): Absorption current Ie: True leakage current According to equation (1) above, the true leakage current of the capacitor
Ie is a unique constant that is not affected by time, but
Measuring this value requires long charging. Therefore, capacitor manufacturers standardize the specified current value after a certain specified period of time has elapsed, and use this as the leakage current standard. The leakage current determination that will be described below relates to the pass/fail determination based on this leakage current standard. According to equation (1), if the DC current i(t) flowing through the capacitor is equal to or less than the leakage current standard after a specified time has elapsed, the pass/fail determination is good. The following explanation will be given with the above in mind.

The first R-S flip-flop circuit (FFa-1 to FFa-n) 10a in FIG. 1 receives the reset signals SIG1 and SIG1 in FIG. 2 when the system power is turned on.
2, the output Q is "0", and the second R-
S flip-flop circuit FFb-1~n)10
b is the FFb set signal SIG2,2 in FIG.
1, the output Q becomes "1".

At the start of measurement, charging time signals TIM1 and TIM2
Relay contacts (rl ₁ -1 to n) 4 become a closed circuit,
Test capacitors (CX1 to n) 5 and resistors (R
1 to n) 7, a direct current i(t) is generated that flows to the capacitor. The DC current i(t) flowing through the capacitor is converted into a DC voltage V(t) by the current-voltage converter circuit (CONV1 to CONVn) 6, and the following relational expression (2) is obtained.

i(t)∞V(t)...(2) From now on, the DC current i(t) flowing through the capacitor is treated as a DC voltage V(t) that has been converted from current to voltage, and the value of the DC current at a certain time t is can be expressed as a DC voltage Vt. Measurement reference value circuit REF
Reference numeral 9 denotes a circuit that can generate a voltage output Vvef corresponding to the DC voltage Vt as the value of the leakage current standard, and any leakage current standard can be manually set.

Therefore, the comparator circuit output (COMPA1 to n)
The output of 8 is V(t)> in section T of charging time TIM1.
If Vvef, comparison judge circuit (COMPA1~n)
If V(t)<Vvef, the output of the comparator circuit (COMPA1-n) 8 is "0". Figure 3 shows the relationship between the outputs of each circuit when V(t), which is the conversion of the DC current i(t) flowing through the capacitor, is a good product with respect to the DC voltage Vref, which is the conversion of the leakage current standard value, after T time has elapsed. is expressed against the time axis.

Here, the DC current V(t) flowing through the electrolytic capacitors under test (CX1 to n) 5 during the specified time interval T initially flows beyond the leakage current standard Vref, and the output b of the comparator becomes "1". FFa output c is also “1”
Therefore, LEDa state c is when the LEDab power is turned on in Figure 2.
Although the TIM2c turns on, the leakage current drops below the leakage current specification before the end of the measurement is judged, so the comparative judgment output b becomes ``0'' and the FFa output c becomes ``0'' before the end of the measurement is judged. , the state c of LEDa is turned off. Thereafter, even after the fall of the FFa hold signal SIG3 in FIG. 2, that is, the end of the measurement and the determination, the LED _a remains off until the next reset.

FIG. 4 shows the relationship of each circuit output with respect to the time axis when the DC current flowing through the capacitor is defective with respect to the leakage current specification. Here, the electrolytic capacitor under test (CX1
~n) Since the DC current V(t) flowing through 5 is higher than the leakage current standard Vref from the start of measurement until the measurement end judgment, the comparator output b continues to be “1”, and therefore the FFa output also “1” and
The output of the LED is also lit. From now on, FF in Figure 2
Even after the a hold signal SIG3 falls (measurement completion/judgment), LED _a remains lit until the next reset.

Next, to explain the determination of the presence or absence of a disconnection with reference to Figures 3 and 4, the flip-flop circuit (FFb-
The output Q of 1 to n) 10b is set to "1" immediately after the power is turned on by the FFb set signal SIG2a in Fig. 2, but if there is no disconnection in the electrolytic capacitor under test at the start of measurement, there will be an inrush current at that moment. The current and current-voltage converter output are expressed by the following equation.

I=V/Rs∞Vt Due to Vt in the above equation, the comparator output also rises rapidly, so the flip-flop circuit (FFb-1
~n) A reset input is input to the R terminal, and the FFb output d becomes “0” from that moment on, as shown in Figure 2.
Even when the LEDa, b power-on signal TIM2c becomes "1", the LEDs b, e continue to be turned off.

Figure 5 shows a case where there is a disconnection, but in this case no current flows through the electrolytic capacitors (CX1 to n) 5 under test, and therefore a flip occurs as shown in Figure 5c.
Since no reset input is input to the R terminal of the flop circuit (FFb-1 to n) 10b, the output Q
continues to be in the "1" state from the start of measurement until reset, and LEDs b and d start lighting in response to the power-on signal TIM2c of LEDa and b in FIG. 2 and continue to be lit until reset.

By changing the starting color of LEDa and LEDb as described above, it is easy to distinguish between leakage current defects and disconnection defects, and the number of test electrolytic capacitors that can be processed at one time is By making connections, you can make decisions freely. As described above, with this invention, it is possible to simultaneously determine whether the leakage current of an electrolytic capacitor is acceptable or disconnected.
And since it can be determined by turning on and off the light emitting diode, processing time can be significantly shortened.
Furthermore, it is possible to construct an inexpensive device that is easy to maintain.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention. FIG. 2 is a timing and signal relationship diagram for operating the circuit of the present invention. Figure 3 is a circuit characteristic diagram when the electrolytic capacitor has good leakage current. Figure 4 is a circuit characteristic diagram in the case of a leakage current failure of an electrolytic capacitor. Fig. 5 is a circuit characteristic diagram when there is a break in the electrolytic capacitor. 1...DC measurement power supply E1, 2...Charging time signal
TIM1, 3...Relay RL1, 4...Relay contact (rl ₁ -1~n), 5...Electrolytic capacitor under test (CX
1~n), 6...Current-voltage converter (CONV1~
n), 7...Resistance (R1~n), 8...Comparison judge (COMPA1~n), 9...Measurement reference value circuit REF,
10a, b...R-S flip-flop circuit (FFa-1~n, FFb-1~n), 11a, b...
...(ORa-1~n, ORb-1~n), 12...Reset signal SIG1, 13...FFa hold signal
SIG3, 14a, b...Inverter circuit (INVa
-1~n, INVb-1~n), 15a, b...Resistance, (Ra-1~n, Rb-1~n), 16a, b...
...Light emitting diode (LEDa-1~n, LEDb-1
~n), 17...LEDa,b power-on signal TIM2,
18...Relay RL ₂ , 19...Relay contact rl ₂ , 2
0...Light-emitting diode drive power supply _E2 , 21...FF
b Set signal SIG2.

Claims (1)

[Scope of utility model registration request] a current-to-voltage converter circuit connected to one terminal of the electrolytic capacitor; and a comparator circuit connected to the output of the current-to-voltage converter circuit; Connect the output of the comparison/judgment device to the S terminal, connect the output terminal of the 2-input OR circuit to the R terminal, connect a reset signal and a hold signal to each input terminal of the 2-input OR circuit, and The output of the comparator circuit is connected to the R terminal of the second R-S flip-flop circuit, and the output terminal of the 2-input OR circuit is connected to the S terminal, and each input terminal of the 2-input OR circuit is connected to the R terminal of the second R-S flip-flop circuit. 1. A device for determining the leakage current quality and disconnection of an electrolytic capacitor, characterized in that it has a circuit in which a reset signal is connected to the Q terminal, and an inverter circuit is connected to the Q terminal via a resistor.